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verilog - always_comb 构造的 Systemverilog 问题

转载 作者:行者123 更新时间:2023-12-05 08:44:35 28 4
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我对这段 SystemVerilog 代码有疑问。这是代码:

module mult ( multiplicand, multiplier, Product, clk, clear, Startm, endm );

input [31:0] multiplicand;
input [31:0] multiplier ;
input clk;
input clear;
input Startm;

output logic [63:0] Product;
output logic endm;


enum logic [1:0] { inicio, multiplicar, nao_multiplicar, fim } estados;
logic [1:0] state;

logic [31:0] mplier;
logic [31:0] mplier_aux;
logic [31:0] mcand ;
logic [31:0] mcand_aux;
logic [63:0] Prod ;
logic [63:0] Prod_aux;
logic [5:0] cont;
logic [5:0] cont_aux;

initial begin
mplier = multiplier;
mplier_aux = multiplier;
mcand = multiplicand;
mcand_aux = multiplicand;
Prod = 0;
Prod_aux = 0;
state = inicio;
cont = 0;
cont_aux = 0;
end

always_ff @( posedge clk )
begin
if( clear )
begin
state <= inicio;
end
else if ( Startm )
begin
case( state )
inicio :
begin
if( mplier[0] == 0 )
begin
state <= nao_multiplicar;
end
else if( mplier[0] == 1 )
begin
state <= multiplicar;
end
end
multiplicar :
begin
if( cont == 32 )
state <= fim;
else if( mplier[0] == 0 )
begin
state <= nao_multiplicar;
end
else if( mplier[0] == 1 )
begin
state <= multiplicar;
end
end
nao_multiplicar:
begin
if( cont == 32 )
state <= fim;
else if( mplier[0] == 0 )
begin
state <= nao_multiplicar;
end
else if( mplier[0] == 1 )
begin
state <= multiplicar;
end
end
fim:
begin
state <= inicio;
end
endcase
end
end
always_comb
begin
case(state)
inicio:
begin
mplier = multiplier;
mcand = multiplicand;
Prod = 0;
cont_aux = cont + 1;
cont = cont_aux;
end
multiplicar:
begin
mcand_aux = mcand << 1;
mcand = mcand_aux ;
mplier_aux = mplier >> 1;
mplier = mplier_aux ;
Prod_aux = Prod + mcand;
Prod = Prod_aux;
cont_aux = cont + 1;
cont = cont_aux;
end
nao_multiplicar:
begin
cont_aux = cont + 1;
cont = cont_aux;
end
fim:
begin
Product = Prod;
endm = 1;
end
endcase
end
endmodule

我正在尝试使用 32 位输入和 64 位乘积编写一个乘法器布斯算法。发生此错误:

always_comb construct does not infer purely combinational logic

为什么会这样?

最佳答案

always block 中描述组合逻辑时,您必须确保所有变量都已分配给代码中所有路径中的值。否则将推断出闩锁。在传统的 always block 中很容易遗漏这样的东西,因此在 SystemVerilog 中引入了 always_comb block 来明确检查这一点。

在你的例子中,你有一些总线在 case 语句的每个分支中都没有赋值,例如 mcand 在分支 nao_multipcar 中没有赋值fim

有两种解决方案。首先是分配给所有代码分支中的所有变量。

另一种解决方案是在 case 语句之前为 always_comb 中的所有变量写入“默认”值。这样,每次 always_comb block 触发时,每个变量总是会被赋值,并且不会有警告。你的case语句然后只需要处理需要改变的变量:

always_comb
begin
// Defaults (I think I got them all)
mplier = multiplier;
mcand = multiplicand;
Prod_aux = 0;
Prod = 0;
cont_aux = 0;
cont = 0;
Product = 0;
endm = 0;

// Now override the defaults when appropriate
case(state)
inicio:
begin
mplier = multiplier;
mcand = multiplicand;
Prod = 0;
cont_aux = cont + 1;
cont = cont_aux;
end
multiplicar:
begin
mcand_aux = mcand << 1;
mcand = mcand_aux ;
mplier_aux = mplier >> 1;
mplier = mplier_aux ;
Prod_aux = Prod + mcand;
Prod = Prod_aux;
cont_aux = cont + 1;
cont = cont_aux;
end
nao_multiplicar:
begin
cont_aux = cont + 1;
cont = cont_aux;
end
fim:
begin
Product = Prod;
endm = 1;
end
endcase
end

关于verilog - always_comb 构造的 Systemverilog 问题,我们在Stack Overflow上找到一个类似的问题: https://stackoverflow.com/questions/6053338/

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