VHDL 动态范围选择可综合代码

Question

处理复杂的范围选择逻辑。

选择信号的组合太多，选择和连接的范围太多。

我正在寻找一种更好的方法来使其可读，使用从预定义常量和动态输入生成的有意义的变量。

一个简化的例子如下，不确定是否可以合成。

library ieee;
use ieee.std_logic_1164.all;

entity fum is
end entity;

architecture foo of fum is
    signal sel:             std_logic_vector (1 downto 0);
    signal selected_range:  std_logic_vector (5 downto 0);
    signal counter:         std_logic_vector (7 downto 0);

    constant BASE_ADDR_LOW: integer := 2;
    constant RANGE1_BITS  : integer := 2;
    -- this is simplified
    -- dozens of constants involved, and their values can be configured before compiling.
begin

some_process:
    process (sel, counter)
    variable range0_high : integer := BASE_ADDR_LOW;
    variable range1_low  : integer := 0;
    variable range1_high : integer := 0;
    begin

    if (sel = "00") then
    -- this is simpilfied as well
    -- dozens of inputs as sel involved, for 50+ combinations via nested if and case
        range0_high := BASE_ADDR_LOW+1; -- 3
        range1_low  := range0_high+2;   -- 5
        range1_high := range1_low+RANGE1_BITS-1; -- 6

    -- the following elsif will not work as the range1 has 0 bit.
    -- not sure if there is a better way to do this

    -- elsif (sel = "01" ) then
    --  range0_high := BASE_ADDR_LOW+1; -- 5
    --  range1_low  := range0_high+2;   -- N/A
    --  range1_high := range1_low+RANGE1_BITS;  --N/A
    else
        range0_high := BASE_ADDR_LOW;   -- 2
        range1_low  := range0_high+2;   -- 4
        range1_high := range1_low+RANGE1_BITS; --6
    end if;

    -- using variables in range
    selected_ranges <= counter(range1_high downto range1_low) & counter(range0_high downto 0);

    end process;
end architecture;

如果某些字段可能为 0 位，是否有任何方法可以生成可综合代码？

-- e.g. range0_high = 5, range1_* not in use
-- selected_ranges <= *nothing &* counter(5 downto 0);

Answer 1

这不是 Minimal, Complete, and Verifiable example .不管你想多了这个问题。

您的“selected_ranges”是多路复用器，具有两个可能的值，具体取决于是否 sel = "00"。

library ieee;
use ieee.std_logic_1164.all;

entity fum is
end entity;

architecture foo of fum is
    signal sel:             std_logic_vector (1 downto 0);
    signal selected_range:  std_logic_vector (5 downto 0);
    signal counter:         std_logic_vector (7 downto 0);
begin
some_process:
    process (sel, counter)
    begin
        if sel = "00" then
            selected_range <= counter (6 downto 5) & counter (3 downto 0);
        else 
            selected_range <= counter (6 downto 4) & counter (2 downto 0);
        end if;
    end process;
end architecture;

这段代码分析、阐述和运行，通过给"00"的sel添加一个初值并重做，表明两个备选表达式的长度是正确的。

注意 selected_range 的高两位和低三“位”在两种情况下都是相同的，这将在合成中变得更加简化。

所以，是的，您的代码符合综合条件，不，它不是动态范围的(只有一个“位”可以根据 sel 不同，它们代表一个 2:1 多路复用器由查看 sel 的两个输入门驱动。

您只是选择了一种困难的方式来表达您的代码的作用。 (而且这里的表述还是冗长)。