vhdl:warning: 通用整数边界必须是数字文字或属性

Question

为什么下面的代码会在行中生成错误消息“vhdl:warning: universal integer bound must be numeric literal or attribute”:“type mem_type is array ((2**ADDR_WIDTH)-1 downto) of std_logic_vector ( DATA_WIDTH-1 下降到 0);"我该如何解决？

library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;

entity bus_fifo_mem is
    generic(
        ADDR_WIDTH     : integer := 32;
        DATA_WIDTH     : integer := 32;
        ENABLE_BYPASS  : integer := 1
    );
    port(
        clk    : in    std_logic;
        raddr  : in    std_logic_vector(ADDR_WIDTH-1 downto 0);
        re     : in    std_logic;
        waddr  : in    std_logic_vector(ADDR_WIDTH-1 downto 0);
        we     : in    std_logic;
        din    : in    std_logic_vector(DATA_WIDTH-1 downto 0);
        dout   : out   std_logic_vector(DATA_WIDTH-1 downto 0)        
    );
end entity;

architecture rtl of bus_fifo_mem is
    signal     rdata  : std_logic_vector(DATA_WIDTH-1 downto 0);
    signal     din_r  : std_logic_vector(DATA_WIDTH-1 downto 0);
    signal     bypass : std_logic;

    -- VERILOG
    --reg [DATA_WIDTH-1:0] mem[(1<<ADDR_WIDTH)-1:0];

    type mem_type is array ((2**ADDR_WIDTH)-1 downto 0) 
                  of std_logic_vector (DATA_WIDTH-1 downto 0);

    signal mem : mem_type := (others => (others => '0'));

begin

process(clk)
begin
    if (clk = '1' and clk'event) then

        if (we = '1') then
            mem(to_integer(unsigned(waddr))) <= din;
        end if;

        if (re = '1') then
           rdata <= mem(to_integer(unsigned(raddr)));
        end if;

    end if;
end process;


end architecture;

Answer 1

使用这个:

type mem_type is array (integer'(2) ** ADDR_WIDTH - 1 downto 0) 
          of std_logic_vector(DATA_WIDTH-1 downto 0);

取而代之的是:

type mem_type is array ((2**ADDR_WIDTH)-1 downto 0) 
                  of std_logic_vector (DATA_WIDTH-1 downto 0);

完整的工作示例:

library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;

entity bus_fifo_mem is
    generic(
        ADDR_WIDTH     : integer := 32;
        DATA_WIDTH     : integer := 32;
        ENABLE_BYPASS  : integer := 1
    );
    port(
        clk    : in    std_logic;
        raddr  : in    std_logic_vector(ADDR_WIDTH-1 downto 0);
        re     : in    std_logic;
        waddr  : in    std_logic_vector(ADDR_WIDTH-1 downto 0);
        we     : in    std_logic;
        din    : in    std_logic_vector(DATA_WIDTH-1 downto 0);
        dout   : out   std_logic_vector(DATA_WIDTH-1 downto 0)        
    );
end entity;

architecture rtl of bus_fifo_mem is
    signal     rdata  : std_logic_vector(DATA_WIDTH-1 downto 0);
    signal     din_r  : std_logic_vector(DATA_WIDTH-1 downto 0);
    signal     bypass : std_logic;

    -- VERILOG
    --reg [DATA_WIDTH-1:0] mem[(1<<ADDR_WIDTH)-1:0];

    type mem_type is array (integer'(2) ** ADDR_WIDTH - 1 downto 0) 
          of std_logic_vector(DATA_WIDTH-1 downto 0);

    signal mem : mem_type := (others => (others => '0'));

begin

process(clk)
begin
    if (clk = '1' and clk'event) then

        if (we = '1') then
            mem(to_integer(unsigned(waddr))) <= din;
        end if;

        if (re = '1') then
           rdata <= mem(to_integer(unsigned(raddr)));
        end if;

    end if;
end process;


end architecture;