与 "<>"运算符凿部分批量连接

Question

我在与 <> 进行部分批量连接时遇到问题。我在书上看到Digital Design with Chisel (4.3 批量连接)。允许连接具有部分匹配信号的两个束。

我目前正在研究 chisel3.2。它似乎不起作用，并且在使它振作起来的过程中报告chisel3.internal.ChiselException: left (AnonymousBundle(IO io in Fetch)) 和源 (AnonymousBundle(IO io in Decode)) 之间的连接失败 @.regB: Left Record missing field (regB).

这是否在某些版本中发生了变化？

如果改了，我们现在怎么做偏连接呢？

这是测试代码(不要介意模块，只是为了保持信号不优化):

class Fetch extends Module {
val io = IO(new Bundle {
val instr = Output(UInt(32.W))
val pc = Output(UInt(32.W))
})
  val r = RegInit(0.U(32.W))
  r := r + 1.U
  io.pc := r
  io.instr := r+1.U
}
class Decode extends Module {
val io = IO(new Bundle {
val instr = Input(UInt(32.W))
val pc = Input(UInt(32.W))
val aluOp = Output(UInt(5.W))
val regA = Output(UInt(32.W))
val regB = Output(UInt(32.W))
})
  io.aluOp := io.pc
  io.regA := io.instr
  io.regB := io.instr
}
class Execute extends Module {
val io = IO(new Bundle {
val aluOp = Input(UInt(5.W))
val regA = Input(UInt(32.W))
val regB = Input(UInt(32.W))
val result = Output(UInt(32.W))
})
 io.result := io.regA
  when(io.aluOp > 10.U){
    io.result := io.regB
  }
}

object MAIN{
 def main(args:Array[String]):Unit = {
    Driver.execute(Array(""),()=>new Module{
      val io = IO(new Bundle{
        val result = Output(UInt(32.W))
      })
      val fetch = Module(new Fetch())
      val decode = Module(new Decode())
      val execute = Module(new Execute)
      fetch.io <> decode.io
      decode.io <> execute.io
      io <> execute.io
    })
 }
}

Answer 1

链接:chisel3-vs-chisel2

In Unsupported constructs Chapter:

• In Chisel2, bulk-connects <> with unconnected source components do not update connections from the unconnected components.
• In Chisel3, bulk-connects strictly adhere to last connection semantics and unconnected OUTPUTs will be connected to INPUTs resulting in the assignment of random values to those inputs.

很抱歉，我还没有完全了解如何在 Chisel3 中使用 <>。在我看来，您应该避免在 Chisel3 中使用 <>。

这是一个在 Chisel3 中可用的示例。

Code is from here.

import Chisel.Queue
import chisel3._
import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
import chisel3.util.Decoupled
import layered.stage.ElkStage

class MyQueue extends Module {
    // Example circuit using a Queue
    val io = IO(new Bundle {
        val in = Flipped(Decoupled(UInt(8.W)))
        val out = Decoupled(UInt(8.W))
    })
    val queue = Queue(io.in, 2)  // 2-element queue
    io.out <> queue
}

object MyQueue extends App{
    (new ChiselStage).emitVerilog(new MyQueue,Array("-td", "vout"))
    
    // gengerate graph file and it can be viewed by using IDEA plugin named EasySocHDL
    (new ElkStage).execute(
        Array("-td", "vout", "--lowFir"),
        Seq(ChiselGeneratorAnnotation(() => new MyQueue))
    )
}