vhdl - 有没有办法在 ISim 中显示变量？

Question

我正在尝试监视此变量的状态:

shared variable Div16 : integer := 0;

但我在 ISim 中收到此错误:

ISim does not yet support tracing of VHDL variables.

能否在测试台文件中将变量转换为信号？或者有没有其他方法可以将这个值的变化显示为波形？

完整代码:

entity MAIN_UART is
  generic (
    DIVISOR: natural := 120 -- DIVISOR = 50,000,000 / (16 x BAUD_RATE)
    -- 9600 -> 120
     -- 19200 -> 60
  );
  port (
    CLK: in std_logic;        -- clock
    RST: in std_logic         -- reset
  );
end MAIN_UART;

architecture Behavioral of MAIN_UART is

    signal Top16: std_logic; -- 1 clk spike at 16x baud rate    
    shared variable Div16 : integer := 0;

--  constant COUNTER_BITS : natural := integer(ceil(log2(real(DIVISOR))));

begin

-- --------------------------
-- Clk16 Clock Generation
-- --------------------------
    process (RST, CLK)
    begin
        if RST='1' then
            Top16 <= '0';  --good
            Div16 := 0;
        elsif rising_edge(CLK) then
            Top16 <= '0';
                if Div16 = Divisor then
                    Div16 := 0;
                    Top16 <= '1';  --good
                else
                    Div16 := Div16 + 1;
                end if;
        end if;
    end process;

end Behavioral;

Answer 1

您可以添加:

signal Div16_signal : integer := 0;

然后在您的流程结束时添加:

Div16_signal <= Div16;