performance - 关于超线程中 L1 Cache 的自适应模式

Question

我是一名学生，最近在研究超线程。我对这个功能有点困惑——L1 数据缓存上下文模式。

在 architecture optimization manual ，描述了 L1 缓存可以在两种模式下运行:

一级缓存可以根据上下文 ID 位以两种模式运行:

共享模式:L1 数据缓存由两个逻辑处理器完全共享。

自适应模式:在自适应模式下，使用页目录的内存访问在共享 L1 数据缓存的逻辑处理器之间被完全映射。

但是，我很好奇缓存如何根据描述在自适应模式下进行分区。

Answer 1

在英特尔架构上，L1 Context ID 的值为 1表示 L1 数据缓存模式可以设置为自适应模式或共享模式，而值为 0 表示不支持此功能。查看IA32_MISC_ENABLE MSR Bit 24的定义(L1 数据缓存上下文模式)了解详情。
根据 Intel® 64 and IA-32 Architectures Developer's Manual: Vol. 3A (第 11 章/缓存控制)，我在下面引用:

分享方式

In shared mode, the L1 data cache is competitively shared between logical processors. This is true even if the logical processors use identical CR3 registers and paging modes. In shared mode, linear addresses in the L1 data cache can be aliased, meaning that one linear address in the cache can point to different physical locations. The mechanism for resolving aliasing can lead to thrashing. For this reason, IA32_MISC_ENABLE[bit 24] = 0 is the preferred configuration for processors based on the Intel NetBurst microarchitecture that support Intel Hyper-Threading Technology.

自适应模式

Adaptive mode facilitates L1 data cache sharing between logical processors. When running in adaptive mode, the L1 data cache is shared across logical processors in the same core if:

• CR3 control registers for logical processors sharing the cache are identical.

• The same paging mode is used by logical processors sharing the cache.

In this situation, the entire L1 data cache is available to each logical processor (instead of being competitively shared).If CR3 values are different for the logical processors sharing an L1 data cache or the logical processors use different paging modes, processors compete for cache resources. This reduces the effective size of the cache for each logical processor.Aliasing of the cache is not allowed (which prevents data thrashing).

我只是猜想对 L1 数据缓存进行分区没有明确的方法。