mips - Xilinx 设计的最小时钟周期随着输入的变化而不断变化

Question

我使用 VHDL 在 Xilinx 中设计了一个 MIPS 单周期处理器。抽象设计是基于Patterson和Henessy的书提供的理论。完成设计后，我运行了一些汇编代码来检查它的功能并给出了预期的结果。我的问题是设计总结报告(“.SYR”文件)中的“TIMING SUMMARY”。每次我更改存储在指令存储器(这是我的 ROM)中的汇编代码时，单周期处理器的最小时钟周期都会不断变化。不太明白是什么原因？

Timing Summary:---------------Speed Grade: -4   Minimum period: 17.561ns (Maximum Frequency: 56.945MHz)   Minimum input arrival time before clock: No path found   Maximum output required time after clock: 16.296ns   Maximum combinational path delay: No path foundTiming Detail:--------------All values displayed in nanoseconds (ns)=========================================================================Timing constraint: Default period analysis for Clock 'clk'  Clock period: 17.561ns (frequency: 56.945MHz)  Total number of paths / destination ports: 6965792 / 616-------------------------------------------------------------------------Delay:               17.561ns (Levels of Logic = 22)  Source:            MIPS_processor_unit/Datapath_comp/PC_reg/q_5_1 (FF)  Destination:       MIPS_processor_unit/Datapath_comp/RegF/memory_0_0 (FF)  Source Clock:      clk rising  Destination Clock: clk rising  Data Path: MIPS_processor_unit/Datapath_comp/PC_reg/q_5_1 to MIPS_processor_unit/Datapath_comp/RegF/memory_0_0                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------    FDCE:C->Q             2   0.591   0.622  MIPS_processor_unit/Datapath_comp/PC_reg/q_5_1 >>(MIPS_processor_unit/Datapath_comp/PC_reg/q_5_1)     LUT2_L:I0->LO         1   0.704   0.104  Instruction_memory_unit/Mrom_Instruction_out391220_SW0 (N1361)     LUT4:I3->O            3   0.704   0.535  Instruction_memory_unit/Mrom_Instruction_out391236_SW0 (N141)     LUT4:I3->O           17   0.704   1.051  Instruction_memory_unit/Mrom_Instruction_out391236 (Instruction_tl_s)     MUXF5:S->O            2   0.739   0.526  MIPS_processor_unit/Datapath_comp/RegF/mux8_8_f5 (MIPS_processor_unit/Datapath_comp/RegF/mux8_8_f5)     LUT4:I1->O            1   0.704   0.000  MIPS_processor_unit/Datapath_comp/ALUSrc_mux/y1_F (N276)     MUXF5:I0->O           3   0.321   0.610  MIPS_processor_unit/Datapath_comp/ALUSrc_mux/y1 (MIPS_processor_unit/Datapath_comp/ALU_2nd_input_s)     LUT2:I1->O            1   0.704   0.000  MIPS_processor_unit/Datapath_comp/ALU_comp/Msub_y_sig_addsub0001_lut (MIPS_processor_unit/Datapath_comp/ALU_comp/Msub_y_sig_addsub0001_lut)     MUXCY:S->O            1   0.464   0.000  MIPS_processor_unit/Datapath_comp/ALU_comp/Msub_y_sig_addsub0001_cy (MIPS_processor_unit/Datapath_comp/ALU_comp/Msub_y_sig_addsub0001_cy)     MUXCY:CI->O           1   0.059   0.000  MIPS_processor_unit/Datapath_comp/ALU_comp/Msub_y_sig_addsub0001_cy (MIPS_processor_unit/Datapath_comp/ALU_comp/Msub_y_sig_addsub0001_cy)     MUXCY:CI->O           1   0.059   0.000  MIPS_processor_unit/Datapath_comp/ALU_comp/Msub_y_sig_addsub0001_cy (MIPS_processor_unit/Datapath_comp/ALU_comp/Msub_y_sig_addsub0001_cy)     MUXCY:CI->O           1   0.059   0.000  MIPS_processor_unit/Datapath_comp/ALU_comp/Msub_y_sig_addsub0001_cy (MIPS_processor_unit/Datapath_comp/ALU_comp/Msub_y_sig_addsub0001_cy)     MUXCY:CI->O           1   0.059   0.000  MIPS_processor_unit/Datapath_comp/ALU_comp/Msub_y_sig_addsub0001_cy (MIPS_processor_unit/Datapath_comp/ALU_comp/Msub_y_sig_addsub0001_cy)     MUXCY:CI->O           1   0.059   0.000  MIPS_processor_unit/Datapath_comp/ALU_comp/Msub_y_sig_addsub0001_cy (MIPS_processor_unit/Datapath_comp/ALU_comp/Msub_y_sig_addsub0001_cy)     MUXCY:CI->O           0   0.059   0.000  MIPS_processor_unit/Datapath_comp/ALU_comp/Msub_y_sig_addsub0001_cy (MIPS_processor_unit/Datapath_comp/ALU_comp/Msub_y_sig_addsub0001_cy)     XORCY:CI->O           1   0.804   0.424  MIPS_processor_unit/Datapath_comp/ALU_comp/Msub_y_sig_addsub0001_xor (MIPS_processor_unit/Datapath_comp/ALU_comp/y_sig_addsub0001)     LUT4:I3->O            1   0.704   0.000  MIPS_processor_unit/Datapath_comp/ALU_comp/y_sig_mux0000_f5_G (N237)     MUXF5:I1->O         259   0.321   1.334  MIPS_processor_unit/Datapath_comp/ALU_comp/y_sig_mux0000_f5 (Output_address_0_OBUF)     RAM32X1S:A0->O        1   1.025   0.499  Data_memory_unit/Mram_data_mem1 (N10)     LUT3:I1->O            1   0.704   0.000  inst_LPM_MUX_6 (inst_LPM_MUX_6)     MUXF5:I0->O           1   0.321   0.000  inst_LPM_MUX_4_f5 (inst_LPM_MUX_4_f5)     MUXF6:I0->O           1   0.521   0.455  inst_LPM_MUX_2_f6 (Read_data_tl_s)     LUT3:I2->O            8   0.704   0.000  MIPS_processor_unit/Datapath_comp/WB_mux/y1 (MIPS_processor_unit/Datapath_comp/write_data_s)     FDCE:D                    0.308          MIPS_processor_unit/Datapath_comp/RegF/memory_0_0    ----------------------------------------    Total                     17.561ns (11.401ns logic, 6.160ns route)                                       (64.9% logic, 35.1% route)=========================================================================

Timing Summary:---------------Speed Grade: -4   Minimum period: 13.551ns (Maximum Frequency: 73.798MHz)   Minimum input arrival time before clock: No path found   Maximum output required time after clock: 14.466ns   Maximum combinational path delay: No path foundTiming Detail:--------------All values displayed in nanoseconds (ns)=========================================================================Timing constraint: Default period analysis for Clock 'clk'  Clock period: 13.551ns (frequency: 73.798MHz)  Total number of paths / destination ports: 256927 / 278-------------------------------------------------------------------------Delay:               13.551ns (Levels of Logic = 13)  Source:            MIPS_processor_unit/Datapath_comp/PC_reg/q_6 (FF)  Destination:       MIPS_processor_unit/Datapath_comp/PC_reg/q_2 (FF)  Source Clock:      clk rising  Destination Clock: clk rising  Data Path: MIPS_processor_unit/Datapath_comp/PC_reg/q_6 to MIPS_processor_unit/Datapath_comp/PC_reg/q_2                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     FDCE:C->Q            71   0.591   1.354  MIPS_processor_unit/Datapath_comp/PC_reg/q_6 (MIPS_processor_unit/Datapath_comp/PC_reg/q_6)     LUT3_D:I1->O          8   0.704   0.761  Instruction_memory_unit/Mrom_Instruction_out4711110 (N91)     LUT4:I3->O           17   0.704   1.051  Instruction_memory_unit/Mrom_Instruction_out43111_2 (Instruction_memory_unit/Mrom_Instruction_out43111_1)     MUXF5:S->O            1   0.739   0.000  MIPS_processor_unit/Datapath_comp/RegF/mux3_7_f5_0 (MIPS_processor_unit/Datapath_comp/RegF/mux3_7_f51)     MUXF6:I0->O           1   0.521   0.424  MIPS_processor_unit/Datapath_comp/RegF/mux3_5_f6_0 (MIPS_processor_unit/Datapath_comp/RegF/mux3_5_f61)     LUT4:I3->O            1   0.704   0.424  MIPS_processor_unit/Datapath_comp/RegF/read_data_11 (MIPS_processor_unit/Datapath_comp/read_data_1_s)     LUT4:I3->O            1   0.704   0.000  MIPS_processor_unit/Datapath_comp/ALU_comp/Maddsub_y_sig_addsub0000_lut (MIPS_processor_unit/Datapath_comp/ALU_comp/Maddsub_y_sig_addsub0000_lut)     MUXCY:S->O            1   0.464   0.000  MIPS_processor_unit/Datapath_comp/ALU_comp/Maddsub_y_sig_addsub0000_cy (MIPS_processor_unit/Datapath_comp/ALU_comp/Maddsub_y_sig_addsub0000_cy)     MUXCY:CI->O           1   0.059   0.000  MIPS_processor_unit/Datapath_comp/ALU_comp/Maddsub_y_sig_addsub0000_cy (MIPS_processor_unit/Datapath_comp/ALU_comp/Maddsub_y_sig_addsub0000_cy)     MUXCY:CI->O           1   0.059   0.000  MIPS_processor_unit/Datapath_comp/ALU_comp/Maddsub_y_sig_addsub0000_cy (MIPS_processor_unit/Datapath_comp/ALU_comp/Maddsub_y_sig_addsub0000_cy)     MUXCY:CI->O           0   0.059   0.000  MIPS_processor_unit/Datapath_comp/ALU_comp/Maddsub_y_sig_addsub0000_cy (MIPS_processor_unit/Datapath_comp/ALU_comp/Maddsub_y_sig_addsub0000_cy)     XORCY:CI->O          18   0.804   1.072  MIPS_processor_unit/Datapath_comp/ALU_comp/Maddsub_y_sig_addsub0000_xor (MIPS_processor_unit/Datapath_comp/write_data_s)     LUT4_D:I3->O          5   0.704   0.637  MIPS_processor_unit/Controller_comp/PCSrc9 (MIPS_processor_unit/Controller_comp/PCSrc9)     LUT4:I3->O            1   0.704   0.000  MIPS_processor_unit/Datapath_comp/Jump_mux/y1 (MIPS_processor_unit/Datapath_comp/Next_PC_1_s)     FDCE:D                    0.308          MIPS_processor_unit/Datapath_comp/PC_reg/q_6    ----------------------------------------    Total                     13.551ns (7.828ns logic, 5.723ns route)                                       (57.8% logic, 42.2% route)=========================================================================

可以看出，我给了我的 Instruction_memory_unit 两个不同的汇编代码和单周期处理器更改的最短周期。这些是我的疑问:

1) 每次我更改汇编代码时，xilinx 是否会根据我在汇编代码中指定的指令评估关键路径？如果"is"，那么我应该如何获得设计的一般最短期限？

2) 我有 RegF 作为我的寄存器文件，它基本上是包含 MIPS 处理器的 32 个寄存器的 RAM。我无法理解的是，在这两个时序摘要中，“门延迟 + 网络延迟”是不同的。理论上，作为内存的寄存器文件不应该有固定的读取时间吗？

Answer 1

它可能会将您的 ROM 合成为门或 LUT 或 SRL16。 ...检查设备使用情况(就在 .syr 文件中的计时报告之前)以查看它是否正在为 ROM 使用 block 内存 - 它可能不是。

事实上，根据时序报告，这似乎确实是问题所在:那里有很多 LUT，但没有 BRAM 的迹象。

如果这是问题所在，请在 Xilinx 约束指南中查找“attribute ram_style=blockram”(我的拼写/语法可能略有错误)- 如果将其应用于包含 ROM 的阵列，您也许能够克服这个问题.一旦数据在内存中，时序应该更加稳定。

请注意，BlockRams 是同步的:您在一个时钟周期内提供地址，并在一个周期后获取内容。如果这不符合您的流水线模型，您将不得不重新考虑，以便让综合在 block 内存中实现 ROM。