vhdl - 我如何取 std_logic_vector 的绝对值？在 VHDL 中

Question

我不知道如何取两个 std_logic_vector(31 downto 0) 的绝对值；

这是代码的示例:

library ieee;
use ieee.std_logic_1164.all;        
use ieee.numeric_std.all;       -- for the signed, unsigned types and arithmetic ops
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
...
...
port (  
    X: in std_logic_vector(31 downto 0); 
    Y: in std_logic_vector(31 downto 0); 
    F: out std_logic_vector(31 downto 0) 
  );

..
..
..
process(X,Y)
 begin
 F <= abs(X-Y)     --this doesnt work

Answer 1

抛弃非标准库包含并使用标准 signed内置 abs 的类型功能:

library ieee;
use ieee.std_logic_1164.all;        
use ieee.numeric_std.all; -- this is the standard package where signed is defined
-- never use non-standard ieee.std_logic_arith and ieee.std_logic_unsigned

...

port (  
  X: in  std_logic_vector(31 downto 0); 
  Y: in  std_logic_vector(31 downto 0); 
  F: out std_logic_vector(31 downto 0) 
);

...

process(X,Y) is
begin
  F <= std_logic_vector(abs(signed(X)-signed(Y)));
end process;

最后一行有很多 [可能不需要] 在 std_logic_vector 之间转换和 signed ，所以如果它对你的设计的其余部分有意义，你可能更喜欢这个界面:

port (  
  X: in  signed(31 downto 0); 
  Y: in  signed(31 downto 0); 
  F: out signed(31 downto 0) 
);

那么最后一行就是:

 F <= abs(X-Y);