vhdl - 对象已使用但未声明？

Question

我有以下 VHDL 代码，它是一个项目的实体:

library ieee;
use ieee.std_logic_1164.all;
library work;
use work.typedef.all;

entity uc is
    port(faaaa: in std_logic_vector(15 downto 0);
          phi: in std_logic;
          isDirect,isRam,jmp,store,NarOut,arpOut:out std_logic);
    end entity uc;

architecture b8 of ua is
    signal   instt : std_logic_vector(15 downto 0);
    signal bit7: std_logic;
        begin
            bit7<='0';
            instt <= faaaa;
            ....
            process(phi) is
            ....
            end process;
end architecture b8;

错误说:

object "faaaa" is used but not declared

我在这里做错了什么？

Answer 1

您的实体名为 uc ，但架构b8是 ua .