vhdl - 在单周期数据路径中加载半字和加载字节

Question

有一个关于在单周期数据路径中实现加载字节而无需更改数据存储器的问题，解决方案如下。

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This is actually quite a realistic question; most memory systems are entirely word-based, and individual bytes are typically only dealt with inside the processor. When you see a “bus error” on many computers, this often means that the processor tried to access a memory address that was not properly word-aligned, and the memory system raised an exception. Anyway, because byte addresses might not be a multiple of 4, we cannot pass them to memory directly. However, we can still get at any byte, because every byte can be found within some word, and all word addresses are multiples of 4. So the first thing we do is to make sure we get the right word. If we take the high 30 bits of the address (i.e., ALUresult[31-2]) and combine them with two 0 bits at the low end (this is what the “left shift 2” unit is really doing), we have the byte address of the word that contains the desired byte. This is just the byte’s own address, rounded down to a multiple of 4. This change means that lw will now also round addresses down to multiples of 4, but that’s OK since non-aligned addresses wouldn’t work for lw anyway with this memory unit. OK, now we get the data word back from memory. How do we get the byte we want out of it? Well, note that the byte’s byte-offset within the word is just given by the low-order 2 bits of the byte’s address. So, we simply use those 2 bits to select the appropriate byte out of the word using a mux. Note the use of big-endian byte numbering, as is appropriate for MIPS. Next, we have to zero-extend the byte to 32 bits (i.e., just combine it with 24 zeros at its high end), because the problem specifies to do so. Actually, this was a slight mistake in the question: in reality, the lbu instruction zero-extends the byte, but lb sign-extends it. Oh, well. Finally, we have to extend the MemtoReg-controlled mux to accept one new input: the zero-extended byte for the lb case. The MemtoReg control signal must be widened to 2 bits. The original 0 and 1 cases change to 00 and 01, respectively, and we add a new case 10 which is only used in the case of lb.

即使在阅读了解释之后，我也不太明白这是如何工作的，尤其是关于将 ALU 结果左移 2 将给出字节地址......这怎么可能？所以如果我想加载一个半字，那么我会做一个左移，我会得到半字的地址？通过修改数据存储器来加载字节、加载半字的更好方法是什么？ (上面的问题限制了我们不能修改数据内存)

Answer 1

原作者似乎只是在从内存中读取的 32 位数据中添加了一个字节多路复用器。该存储器允许完整的 32 位自然对齐加载(lw 指令)，额外的字节多路复用器和零扩展也允许加载字节指令(lbu 指令)。

ALU 结果的左移产生一个字地址，而不是一个字节地址，并解释了信号路由中隐式右移 2 的原因。最终结果只是 ALU 结果的低两位在发送到内存之前被屏蔽(归零)。 ALU 值的两个 LSB 在内存下游馈送到字节多路复用器，允许字内存读取任意字节。

显示的逻辑中没有直接支持加载半字(16 位)，只有字节和完整的 32 位字。但是，您可以使用类似的方法轻松修改字节寻址逻辑以支持字而不是字节(或什至两者)。