riscv - 日航 : what is the "alternate link register" x5 for?

Question

RISC-V 规范 v2.2(JAL 指令，第 15 页)谈到了“标准调用约定”:

The standard software calling convention uses x1 as the return address register and x5 as an alternate link register.

带有以下设计注释:

The alternate link register supports calling millicode routines (e.g., those to save and restore registers in compressed code) while preserving the regular return address register.

什么是替代链接注册？

我知道“链接寄存器”是一个寄存器，用于存储返回时要跳转到的 pc，而毫码/微码是低于 ISA 级别的较低级别的指令格式。是想法 x5用于代替 x1对于围绕“正常调用”的某些(微码/微码)指令，以避免寄存器改组或溢出？你有一个典型的使用例子吗？

在 link registers 上的维基百科文章中添加对备用链接寄存器的解释可能会有所帮助。 ，这是我去寻找额外信息的地方。

Answer 1

通常，毫代码指令不应与普通指令相交，并且需要另一种调用约定来调用毫代码过程( from Waterman's PhD Thesis, page 66 ):

... routines must have an alternate calling convention since the link register must be preserved during their execution. Fortunately, unlike ARM and MIPS, RISC-V’s jump-and-link instruction can write the return address to any integer register, rather than clobbering the ABI-designated link register. Other than that distinction, these millicode routines behave like ordinary procedures

一个更具体的原因，为什么应该保留链接寄存器，是因为使用微码来实现序言和尾声，因此使用常规调用约定会破坏链接寄存器，并会破坏使用微码进行序言/尾声的整个想法。

Is the idea that x5 is used instead of x1 for certain (microcode/millicode) instructions that surround "normal calls" to avoid register shuffling or a spill?

是的......在某种程度上“环绕”这个词。

Would you have a typical usage example?

见 prologue_2 , epilogue_2来自 Waterman's PhD, page 67 的微码例程

00: c919     c.beqz a0, 16
02: 016002ef jal t0, prologue_2
06: 842a     c.mv s0, a0
08: 157d     c.addi a0, -1
0a: ff7ff0ef jal ra, factorial
0e: 02850533 mul a0, a0, s0
12: 0100006f jal x0, epilogue_2
16: 4505     c.li a0, 1
18: 8082     c.jr ra

哪里 prologue_2 :

00: 1141 c.addi sp, -16
02: e406 c.sdsp ra, 8(sp)
04: e022 c.sdsp s0, 0(sp)
06: 8282 c.jr t0

和 epilogue_2 :

00: 60a2 c.ldsp ra, 8(sp)
02: 6402 c.ldsp s0, 0(sp)
04: 0141 c.addi sp, 16
06: 8082 c.jr ra