conditional - 使用稍后在 verilog 中定义的条件变量

Question

假设我有以下实例化
first_mux_input=top.middle.down[i];
second_mux_input=top.middle.down[i+1];
分配向下=(选择[i])？ first_mux_input:second_mux_input;

假设有很多多路复用器，它们的输出进入位于它们下方的多路复用器的输入。

我在定义它之前使用变量“down”。这是合法的，因为 verilog 随后编译所有行而不是按顺序(在这种情况下)？
谢谢

Answer 1

赋值语句不是声明。声明将是:

wire down;

如果您从未像这样声明down，它将被隐式声明。IEEE 1800-2012 第 6.10 节指出:

If an identifier appears on the left-hand side of a continuous assignment statement, and that identifier has not been declared previously in the scope where the continuous assignment statement appears or in any scope whose declarations can be directly referenced from the scope where the continuous assignment statement appears (see 23.9), then an implicit scalar net of default net type shall be assumed. See 10.3 for a discussion of continuous assignment statements.

然后:

See 22.8 for a discussion of control of the type for implicitly declared nets with the `default_nettype compiler directive.

这(我相信)通常意味着 Verilog 中的线和 SystemVerilog 中的逻辑。

现在，就在分配之前使用值而言，这是完全合法的。只要在使用或赋值后不声明即可。