verilog - seg Controller 故障计数器如何解决

Question

module seg_controller(
            clk,
            reset,
            sel,
            seg,);

    input clk;
    input reset;
    output wire [5:0] sel;
    output wire [7:0] seg;

    wire [9:0] count;
    wire [3:0] d_in;

    counter use_counter(clk, reset, count);
    FSM(count, reset, sel, d_in);
    dec_7seg(d_in,seg);

endmodule   

在这部分，我不知道如何将模块相互连接。每个模块都有很多变量，但除了input clk，reset count, d_in 应该如何使用变量。只用电线？

module counter
    (clk,
     reset,
     count);

     input clk;
     input reset;
     output reg [9:0] count;

    always @ (posedge clk)
      begin
            if(reset) count <= 0;
            else        count <= count + 1;
      end

endmodule






module FSM (
            count,
            reset,
            sel,
            d_in);

input [9:0]count;
input reset;
output reg [5:0] sel;
output reg [3:0] d_in;

reg [5:0] state, nextstate;

parameter S0 = 6'b100_000;
parameter S1 = 6'b010_000;
parameter S2 = 6'b001_000;
parameter S3 = 6'b000_100;
parameter S4 = 6'b000_010;
parameter S5 = 6'b000_001;


always @ (*)
      begin
            if(reset) sel = 6'b100_000;
            else if(count == 10'b11_1111_1111)
                state = nextstate;
                 d_in = d_in + 1;   
      end

always @ (*)
    case(state)
        S0: nextstate = S1;
        S1: nextstate = S2;
        S2: nextstate = S3;
        S3: nextstate = S4;
        S4: nextstate = S5;
        S5: nextstate = S0;
        default: nextstate = S0;
    endcase

always @ (*)
    if(state == S0) begin
        sel = S0; end
    else if(state == S1) begin
        sel = S1; end
    else if(state == S2) begin
        sel = S2; end
    else if(state == S3) begin
        sel = S3; end
    else if(state == S4) begin
        sel = S4; end
    else begin
        sel = S5; end

endmodule

在这部分

如果(状态== S0)开始选择 = S0;结束

错误 (10028):无法在 FSM.v(44) 解析网络“sel[4]”的多个常量驱动程序

不知道为什么会出现这个按摩

module dec_7seg(
            d_in,
            seg
            );

input [3:0]d_in;
output [7:0]seg;
wire [3:0]d;

assign d[3] = ~ d_in[3];
assign d[2] = ~ d_in[2];
assign d[1] = ~ d_in[1];
assign d[0] = ~ d_in[0];

assign seg[0] = ~(d[3] & d[2] | d[3] & d[1]);
assign seg[1] = ~(~d[2] & d[1] | d[2] & ~d[1] | d[3] & d[0] | d[1] & ~d[0]);
assign seg[2] = ~(d[3] & ~d[2] | d[3] & d[1] | ~d[3] & d[2] & ~d[1] | d[2] & 
d[1] & ~d[0] | ~d[2] & ~d[1] & ~d[0]);
assign seg[3] = ~(d[3] & d[2] | d[3] & d[1] | ~d[2] & ~d[0] | d[1] & ~d[0]);
assign seg[4] = ~(d[2] & ~d[1] & d[0] | d[3] & ~d[1] | ~d[2] & d[1] & d[0] | 
~d[3] & ~d[2] & ~d[0] | d[2] & d[1] & ~d[0]);
assign seg[5] = ~(~d[3] & d[2] | d[3] & ~d[2] | ~d[1] & d[0] | ~d[2] & ~d[1] 
| ~d[2] & d[0]);
assign seg[6] = ~(~d[3] & d[1] & d[0] | d[3] & ~d[1] & d[0] | d[3] & d[1] & 
~d[0] | ~d[3] & ~d[1]& ~d[0] | ~d[2] & ~d[1] | ~d[2] & ~d[0]);
assign seg[7] = ~(~d[3] & d[1] | d[2] & d[1] | ~d[2] & ~d[0] | d[3] & ~d[2] 
& ~d[1] | ~d[3] & d[2] & d[0]);

endmodule

我想让它工作。但我是verilog的初学者。有太多问题，我不知道为什么。所以我想知道解决那个可怕代码的方向......

Answer 1

你的问题是你在这里被分配了sel

always @ (*)
      begin
            if(reset) sel = 6'b100_000;    // <-- You should assign
                                           //     state and d_in here only
            else if(count == 10'b11_1111_1111)
                state = nextstate;
                 d_in = d_in + 1;   
      end

然后在另一个进程中赋值sel

always @ (*)
    if(state == S0) begin
        sel = S0; end
    else if(state == S1) begin
        sel = S1; end
    else if(state == S2) begin
        sel = S2; end
    else if(state == S3) begin
        sel = S3; end
    else if(state == S4) begin
        sel = S4; end
    else begin
        sel = S5; end

endmodule

我想你希望它在重置时出现在 S0 中，所以你可以试试这个

always @ (*)
    if(state == S0 || reset) begin  // Now you reset sel and assign in 
        sel = S0; end               // the same process
    else if(state == S1) begin
        sel = S1; end
    else if(state == S2) begin
        sel = S2; end
    else if(state == S3) begin
        sel = S3; end
    else if(state == S4) begin
        sel = S4; end
    else begin
        sel = S5; end