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compilation - 请帮我解决 VHDL 编译错误

转载 作者:行者123 更新时间:2023-12-04 16:00:08 25 4
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library IEEE;
use IEEE.std_logic_1164.all;

entity doorlock is
port( reset : in std_logic;
enable : in std_logic;
password : in std_logic_vector (7 downto 0);
door : out std_logic_vector (7 downto 0);
lock : out std_logic;
alarm : out std_logic;
turnoff : out std_logic);
end doorlock;

--password is 10(decimal no.) which is 00010000(binary no.)

architecture DDL of doorlock is
signal err_count : integer range 0 to 5 := 0;

begin
lock <= '0' when (reset = '0');
alarm <= '0' when (reset = '0');
turnoff <= '0' when (reset = '0');
door <= "00000000" when (reset = '0');
lock <= '0' when (enable <= '0');

process(password)
begin
if (password = "-------1") then
door <= "00000000";
elsif (password = "------10") then
door <= "00000001";
elsif (password = "-----100") then
door <= "00000011";
elsif (password = "----1000") then
door <= "00000111";
elsif (password = "---00000") then
door <= "00001111";
elsif (password = "--110000") then
door <= "00011111";
elsif (password = "-1010000") then
door <= "00111111";
elsif (password = "10010000") then
door <= "01111111";
elsif (password = "00010000") then
door <= "11111111";
end if;

err_count <= err_count + 1;
end process;

alarm <= '1' when (err_count = 3);
turnoff <= '1' when (err_count = 5);
lock <= '1' when (door = "11111111" and turnoff = '0' and alarm = '0');

end DDL;

我为制作数字门锁的作业编写了这段代码。这行在我编译时有错误。

lock <= '1' when (door = "11111111" and turnoff = '0' and alarm = '0');

错误如下图

** 错误:D:\modelsim\Door.vhd(53):无法读取输出“警报”。

VHDL 2008 允许读取输出。此功能通过使用 -2008 进行编译来启用。

** 错误:D:\modelsim\Door.vhd(53):无法读取输出“门”。

VHDL 2008 允许读取输出。此功能通过使用 -2008 进行编译来启用。

** 错误:D:\modelsim\Door.vhd(53):无法读取输出“关闭”。

VHDL 2008 允许读取输出。此功能通过使用 -2008 进行编译来启用。

** 错误:D:\modelsim\Door.vhd(55): VHDL 编译器正在退出

我不知道为什么会这样,请帮帮我

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