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vhdl - 通过 VHDL 中不同进程的程序驱动记录元素

转载 作者:行者123 更新时间:2023-12-04 15:40:21 24 4
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在我的架构中,我定义了某种记录类型的信号。每个记录元素仅在一个进程中驱动。

整个记录信号被传递给程序。这些程序稍后将放在一个包中。将记录作为类型“inout”传递会导致所有访问的记录元素解析为“X”。

代码在Modelsim中运行,仅用于验证(无需综合)。

直接驱动记录元素是可行的。

最小的例子;架构标题:

-- Record type
type tr_Data is record
r1_A : std_logic;
r1_B : std_logic;
end record;

-- Signal definition and initialization
signal sr_Data : tr_Data := (
r1_A => '0',
r1_B => '1'
);

架构主体:

-- This process only modifies sr_Data.r1_A
prcss_A: process
procedure proc_Modify_A(signal d: inout tr_Data) is
begin
d.r1_A <= not d.r1_A;
end procedure;
begin
wait for 1 us;
--sr_Data.r1_A <= not sr_Data.r1_A; -- This works
proc_Modify_A(sr_Data); -- This works not
wait for 1 us;
wait;
end process;

-- This process only modifies sr_Data.r1_B
prcss_B: process
procedure proc_Modify_B(signal d: inout tr_Data) is
begin
d.r1_B <= not d.r1_B;
end procedure;
begin
wait for 1.5 us;
--sr_Data.r1_B <= not sr_Data.r1_B; -- This works
proc_Modify_B(sr_Data); -- This works not
wait for 1 us;
wait;
end process;

这是 Modelsim 中的结果:

Modelsim simulation result

我不确定这是否可能。也许还有更好的解决方案来解决我的问题。

谢谢你的帮助!

最佳答案

这个问题说明了为什么提供 minimal, complete, and verifiable exampe对于代码错误是可取的(而不是这里的代码片段)。

创建一个 MCVe:

library ieee;
use ieee.std_logic_1164.all;

entity record_process is
end entity;

architecture foo of record_process is
type tr_Data is record
r1_A: std_logic;
r1_B: std_logic;
end record;
signal sr_Data: tr_Data := (r1_A => '0', r1_B => '1');
begin
prcss_A: -- This process only modifies sr_Data.r1_A
process
procedure proc_Modify_A(signal d: inout tr_Data) is
begin
d.r1_A <= not d.r1_A;
end procedure;
begin
wait for 1 us;
-- sr_Data.r1_A <= not sr_Data.r1_A; -- This works
proc_Modify_A(sr_Data); -- This works not
wait for 1 us;
wait;
end process;

prcss_B: -- This process only modifies sr_Data.r1_B
process
procedure proc_Modify_B(signal d: inout tr_Data) is
begin
d.r1_B <= not d.r1_B;
end procedure;
begin
wait for 1.5 us;
--sr_Data.r1_B <= not sr_Data.r1_B; -- This works
proc_Modify_B(sr_Data); -- This works not
wait for 1 us;
wait;
end process;
MONITOR:
process (sr_Data)
begin
report
LF & HT &
"sr_Data.r1_A = " & std_logic'image(sr_Data.r1_A) &
LF & HT &
"sr_Data.r1_B = " & std_logic'image(sr_Data.r1_B);
end process;
end architecture;

我们看到报告的行为与 OP 的波形相匹配:

record_process.vhdl:44:9:@0ms:(report note):
sr_Data.r1_A = '0'
sr_Data.r1_B = '1'
record_process.vhdl:44:9:@1us:(report note):
sr_Data.r1_A = 'X'
sr_Data.r1_B = '1'
record_process.vhdl:44:9:@1500ns:(report note):
sr_Data.r1_A = 'X'
sr_Data.r1_B = 'X'

“X”是由驱动程序与子程序实际参数关联的方式引起的:

IEEE 标准 1076-2008
4.2 子程序声明
4.2.2.3 信号参数

A process statement contains a driver for each actual signal associated with a formal signal parameter of mode out or inout in a subprogram call. Similarly, a subprogram contains a driver for each formal signal parameter of mode out or inout declared in its subprogram specification.

For a signal parameter of mode inout or out, the driver of an actual signal is associated with the corresponding driver of the formal signal parameter at the start of each call. Thereafter, during the execution of the subprogram body, an assignment to the driver of a formal signal parameter is equivalent to an assignment to the driver of the actual signal.

10.7 过程调用语句

For each formal parameter of a procedure, a procedure call shall specify exactly one corresponding actual parameter. This actual parameter is specified either explicitly, by an association element (other than the actual open) in the association list or, in the absence of such an association element, by a default expression (see 6.5.2).

整体上有一个实际关联的驱动,这里是一个记录类型的信号。

(这也告诉你 Tricky 的答案是有效的,这将实际减少为整体的一个元素。)

还有另一种可能的解决方案
删除参数列表:

architecture fum of record_process is
type tr_Data is record
r1_A: std_logic;
r1_B: std_logic;
end record;
signal sr_Data: tr_Data := (r1_A => '0', r1_B => '1');
begin
prcss_A: -- This process only modifies sr_Data.r1_A
process
procedure proc_Modify_A is
begin
sr_Data.r1_A <= not sr_Data.r1_A;
end procedure;
begin
wait for 1 us;
-- sr_Data.r1_A <= not sr_Data.r1_A; -- This works
proc_Modify_A; -- This works not
wait for 1 us;
wait;
end process;

prcss_B: -- This process only modifies sr_Data.r1_B
process
procedure proc_Modify_B is
begin
sr_Data.r1_B <= not sr_Data.r1_B;
end procedure;
begin
wait for 1.5 us;
--sr_Data.r1_B <= not sr_Data.r1_B; -- This works
proc_Modify_B; -- This works not
wait for 1 us;
wait;
end process;
MONITOR:
process (sr_Data)
begin
report
LF & HT &
"sr_Data.r1_A = " & std_logic'image(sr_Data.r1_A) &
LF & HT &
"sr_Data.r1_B = " & std_logic'image(sr_Data.r1_B);
end process;
end architecture;

产生:

record_process.vhdl:89:9:@0ms:(report note):
sr_Data.r1_A = '0'
sr_Data.r1_B = '1'
record_process.vhdl:89:9:@1us:(report note):
sr_Data.r1_A = '1'
sr_Data.r1_B = '1'
record_process.vhdl:89:9:@1500ns:(report note):
sr_Data.r1_A = '1'
sr_Data.r1_B = '0'

没有任何驱动程序冲突,缺少多个驱动程序(14.7.2 驱动程序)需要在模拟期间解决(14.7.3.4 信号更新)。

14.7.2 驱动程序

Every signal assignment statement in a process statement defines a set of drivers for certain scalar signals. There is a single driver for a given scalar signal S in a process statement, provided that there is at least one signal assignment statement in that process statement and that the longest static prefix of the target signal of that signal assignment statement denotes S or denotes a composite signal of which S is a subelement. Each such signal assignment statement is said to be associated with that driver. Execution of a signal assignment statement affects only the associated driver(s).

最长的静态前缀定义在8. Names:

8.1 总则

A static signal name is a static name that denotes a signal. The longest static prefix of a signal name is the name itself, if the name is a static signal name; otherwise, it is the longest prefix of the name that is a static signal name. ...

最长的静态前缀现在包括记录元素,而不是整体关联的记录类型的实际信号。

这是可能的,因为子程序是一系列语句(4.2 子程序主体)并且过程在 sr_Data 的声明范围内声明(12.1 声明区域,12.2 声明范围,12.3可见性)。

关于vhdl - 通过 VHDL 中不同进程的程序驱动记录元素,我们在Stack Overflow上找到一个类似的问题: https://stackoverflow.com/questions/57975427/

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