arrays - 何时使用 tick(') 进行 Verilog 数组初始化？

Question

数组初始化可以在有或没有 ' 的情况下完成:

int a[8] = '{0,1,2,3,4,5,6,7}; // Packed
int b[8] = {0,1,2,3,4,5,6,7};  // Unpacked

有没有 正确 方式，假设数组使用不可压缩的类型，如 int、string 等？这两种方式似乎都很好。

EDA Playground 上的完整代码示例: http://www.edaplayground.com/x/3Tc

Answer 1

基于 IEEE 1800-2009:

Array assignment patterns (1) have the advantage that they can be used to create assignment pattern expressions of selfdetermined type by prefixing the pattern with a type name. Furthermore, items in an assignment pattern can be replicated using syntax such as '{ n{element} }, and can be defaulted using the default: syntax. However, every element item in an array assignment pattern must be of the same type as the element type of the target array. By contrast, unpacked array concatenations (2) forbid replication, defaulting and explicit typing, but they offer the additional flexibility of composing an array value from an arbitrary mix of elements and arrays.

所以:

int A3[1:3];
int A9[1:9];

A3 = '{1, 2, 3}; #legal
A9 = '{3{A3}};   #illegal
A9 = {A3, 4, 5, A3, 6}; #legal
A9 = '{9{1}}; #legal
A9 = {9{1}}; #illegal