system-verilog - systemverilog 解压数组连接

Question

我正在尝试创建一个像这样的解包数组:

logic [3:0] AAA[0:9];

我想将此数组初始化为以下值:

AAA = '{1, 1, 1, 1, 2, 2, 2, 3, 3, 4};

为了提高效率，我想使用重复结构，但那是事情分崩离析的时候。
这是不可能的，还是我写得不对？任何帮助表示赞赏。

AAA = { '{4{1}}, '{3{2}}, '{2{3}}, 4 };

Answer 1

首先，您使用的构造实际上称为复制运算符。这可能对您将来的搜索有所帮助，例如在 the SystemVerilog LRM 中的搜索。 .

其次，您在最后一个代码块中使用了数组连接而不是数组赋值(注意缺少的撇号 ' )。 LRM 在第 10.10.1 节(未打包的数组连接与数组分配模式的比较)中给出了以下(简单)示例来解释差异:

int A3[1:3];
A3 = {1, 2, 3}; // unpacked array concatenation
A3 = '{1, 2, 3}; // array assignment pattern

LRM 在同一部分中说

...unpacked array concatenations forbid replication, defaulting, and explicit typing, but they offer the additional flexibility of composing an array value from an arbitrary mix of elements and arrays.

int A9[1:9]; 
A9 = {9{1}}; // illegal, no replication in unpacked array concatenation

让我们看看替代方案:数组赋值。在同一部分，LRM 提到

...items in an assignment pattern can be replicated using syntax, such as '{ n{element} }, and can be defaulted using the default: syntax. However, every element item in an array assignment pattern must be of the same type as the element type of the target array.

如果将其转换为数组赋值(通过添加撇号)，您的代码实际上会转换为:

AAA = '{'{1,1,1,1}, '{2,2,2}, '{3,3}, 4};

这意味着 SystemVerilog 解释器只会看到 4 个元素，并且会提示在赋值中给出的元素太少。

在第 10.9.1 节(数组分配模式)中，LRM 对此进行了如下说明:

Concatenation braces are used to construct and deconstruct simple bit vectors. A similar syntax is used to support the construction and deconstruction of arrays. The expressions shall match element for element, and the braces shall match the array dimensions. Each expression item shall be evaluated in the context of an assignment to the type of the corresponding element in the array.

[...]

A syntax resembling replications (see 11.4.12.1) can be used in array assignment patterns as well. Each replication shall represent an entire single dimension.

为了帮助解释上面引用中的粗体文本，LRM 给出了以下示例:

int n[1:2][1:3] = '{2{'{3{y}}}}; // same as '{'{y,y,y},'{y,y,y}}