scala - 在 Chisel 中测试 RegisterFile

Question

我想测试一个寄存器向量(一个 registerFile)。下面是一个读取 registerFile 索引值的函数:-

class ViewRegFile(regnum: Int, size: Int) extends Module {
  val io = IO(new Bundle {
    val registers =  Input(Reg(Vec(regnum,UInt(size.W))))
    val inputs = Input(UInt(size.W))
    val ok = Input(UInt(1.W))
    val values = Output(UInt(size.W))
  })
  val buffer = RegInit(VecInit(Seq.fill(regnum)(0.U(size.W)))) // so we have a reset to buffer regmap
  when(io.ok === 1.U){
  for(i<-0 until regnum) {
  buffer(i)  := io.registers(i)
  }
  }
  val itr = io.inputs
  io.values := buffer(itr)
}

上面的代码采用 registerFile 寄存器，它具有大小为 size 的 regnum 寄存器。我正在使用变量输入索引 registerFile 并通过变量值输出 registerFile 的索引值。

为了测试功能，我在测试平台中创建了一个 registerFile，初始化了 File 的一些值，并希望使用上面编写的函数 ViewRegFile 读取输出。我现在陷入困境，不知道我在实现中哪里出了问题。以下是我尝试制作的测试平台:-

import java.io.File
import chisel3._   //needed to declare testbench (tb) registerFile
import chisel3.iotesters
import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester}

class RegUnitTester(c: ViewRegFile, val regnum: Int, val size:Int) extends PeekPokeTester(c) {
 private val mod = c
val register = RegInit(VecInit(Seq.fill(regnum)(0.U(size.W)))) // tb registerFile
val val1 = 1434.U(size.W)
val val2 = 9082.U(size.W)
register(1) := val1
register(2) := val2 
poke(mod.io.registers, register) //loaded tb registerFile to function registerFile
for(j<- 0 until regnum) {
  poke(mod.io.inputs, j) //desired values from function registerFile
  poke(mod.io.ok,1)
  step(1)
  poke(mod.io.ok,0)
  peek(mod.io.values) } // indexed output
}

object RegTester extends App {
  println("Testing RegFile Viewer")
  iotesters.Driver.execute(Array("--target-dir", "generated", "--generate-vcd-output", "on"), () => new ViewRegFile(4, 16)) {
    c => new RegUnitTester(c,4,16)
  }
}

并且 poke 因错误而失败:

[error] overloaded method value poke with alternatives: 
[error]   (signal: chisel3.Aggregate,value: IndexedSeq[BigInt])Unit <and>
[error]   (signal: chisel3.Bundle,map: Map[String,BigInt])Unit <and>
[error]   [T <: chisel3.Element](signal: T, value: Long)(implicit evidence$10: chisel3.iotesters.Pokeable[T])Unit <and>
[error]   [T <: chisel3.Element](signal: T, value: Int)(implicit evidence$9: chisel3.iotesters.Pokeable[T])Unit <and>
[error]   [T <: chisel3.Element](signal: T, value: BigInt)(implicit evidence$8: chisel3.iotesters.Pokeable[T])Unit <and>
[error]   (path: String,value: Long)Unit <and>
[error]   (path: String,value: Int)Unit <and>
[error]   (path: String,value: BigInt)Unit
[error] poke(mod.io.registers, register)

Answer 1

问题是您在测试仪中使用 Chisel 结构。 Chisel API 调用(包括 RegInit 、 VecInit 、 .U 和 .W )用于构建硬件；在测试人员中，您应该使用纯 Scala 来建模行为。例如:

import java.io.File
import chisel3._   //needed to declare testbench (tb) registerFile
import chisel3.iotesters
import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester}

class RegUnitTester(c: ViewRegFile, val regnum: Int, val size:Int) extends PeekPokeTester(c) {
  private val mod = c
  val register = Array.fill(regnum)(BigInt(0)) // Using BigInt because Int is 32-bit
  register(1) = 1434 // I didn't wrap in BigInt because Scala will convert from Int automatically
  register(2) = 9082 // If you create values that don't fit in 32-bit *signed* Int, wrap in BigInt(...)
  // You can't poke internal values, there is some support for this, see:
  // https://github.com/freechipsproject/chisel3/wiki/Chisel-Memories#loading-memories-in-simulation
  //poke(mod.io.registers, register) //loaded tb registerFile to function registerFile
  for(j<- 0 until regnum) {
    poke(mod.io.inputs, j) //desired values from function registerFile
    poke(mod.io.ok,1)
    step(1)
    poke(mod.io.ok,0)
    peek(mod.io.values) // indexed output
  }
}

object RegTester extends App {
  println("Testing RegFile Viewer")
  iotesters.Driver.execute(Array("--target-dir", "generated", "--generate-vcd-output", "on"), () => new ViewRegFile(4, 16)) {
    c => new RegUnitTester(c,4,16)
  }
}