exception - 为什么ARM异常中prefetch abort和data abort的返回地址不同？

Question

对于预取，返回地址为:
R14_abt = 中止指令的地址 + 4

对于数据中止，返回地址为:
R14_abt = 中止指令的地址 + 8

Answer 1

这些偏移是由于处理器的流水线和获取/解码/执行阶段造成的。
处理器的程序计数器 (PC) 在执行期间的特定点更新。在获取/解码/执行的不同阶段可能会发生异常。
在预取中止的情况下，指令不能(尚未)执行；只有当处理器实际尝试执行指令时才会发生异常(某些预取指令可能不会被执行)。
在数据中止的情况下，指令正在执行，指令的执行导致异常。
来自 ARM 文档:
关于预取中止:

[The prefetch abort exception] Occurs when theprocessor attempts to execute aninstruction that has prefetched froman illegal address, that is, anaddress that the memory managementsubsystem has determined isinaccessible to the processor in itscurrent mode.

... Instructions already in the pipeline continue to execute until the invalid instruction is reached, at which point a prefetch abort is generated.

... because the program counter is not updated at the time the prefetch abort is issued, lr_ABT points to the instruction following the one that caused the exception. The handler must return to lr_ABT – 4

关于数据中止:

[The Data Abort exception] Occurs whena data transfer instruction attemptsto load or store data at an illegaladdress.

When a load or store instruction tries to access memory, the program counter has been updated. A stored value of (pc – 4) in lr_ABT points to the second instruction beyond the address where the exception was generated. When the MMU has loaded the appropriate address into physical memory, the handler should return to the original, aborted instruction so that a second attempt can be made to execute it. The return address is therefore two words (eight bytes) less than that in lr_ABT

所以换句话说，对于数据中止，处理程序必须返回到 lr_ABT – 8 (前面两个字/说明)