Verilog 无符号非恢复除法。语法错误 : "I give up" Icarus Verilog

Question

我想知道为什么我的 Iverilog 编译器会在模块末尾抛出“我放弃”错误。错误是:

DivisionsSchaltwerk.v:64: syntax error I give up

我的 Divisior 的 Verilog 代码使用 AQ 移位无符号非恢复除法算法的更改版本。第 64 列位于 endmodule部分。

module Division(
    input         clock,
    input         start,
    input  [31:0] a,
    input  [31:0] b,
    output [31:0] q,
    output [31:0] r
);
    reg[31:0] AQ;
    reg[31:0] B;
    reg[31:0] R;
    reg[5:0] count;
    reg running;

    assign q = AQ;
    assign r = R;
    
    always @(posedge clock) begin
        if (start) begin
            R <= 0;
            AQ <= a;
            B <= b;
            count <= 6'd32;
            running <= 1;
         end
        else if (count == 0) begin
            running <=0;
            if(R<0) begin
                R <= R + B;
            end
            else begin
                R <= R - B;
            end
        end
        if (running) begin
            if (R<0) begin
                R <= R<<1;
                R[0] <= AQ[32];
                AQ <= AQ<<1;
            end
               if(R<0) begin 
                    AQ[0] <= 0;
                    R <= R + B;
                    count <= count -6'd1;
                end
                else begin
                    AQ[0] <= 1;
                    R <= R - B;
                    count <= count - 6'd1;
                end
            end
            else begin
                R <= R<<1;
                R[0] <= AQ[32];
                AQ <= AQ<<1;
            end
                if(R<0) begin 
                    AQ[0] <= 0;
                    R <= R + B;
                    count <= count -6'd1;
                end
                else begin
                    AQ[0] <= 1;
                    R <= R - B;
                    count <= count - 6'd1;
                end                
endmodule

Answer 1

您的代码有两种类型的错误:

编译错误

编译警告

编译错误是缺少 end在您的 always堵塞。其他模拟器，例如 上的模拟器edaplayground ，产生一个稍微有用(和常见)的错误消息，例如:

endmodule
        |
xmvlog: *E,NOTSTT : expecting a statement [9(IEEE)].

再加上代码缩进不一致，这通常意味着不匹配 begin/end对。此外，您可以使用 emacs自动重新缩进您的代码:

emacs --batch DivisionsSchaltwerk.v -f verilog-batch-indent 

您还会收到编译警告，例如:

            R[0] <= AQ[32];
                     |
xmelab: *W,BNDWRN : Bit-select or part-select index out of declared bounds.

您声明了 AQ如 [31:0]。你真的要使用 AQ[31] ?

这是您的自动缩进 always匹配 begin/end 的 block :

   always @(posedge clock) begin
      if (start) begin
         R <= 0;
         AQ <= a;
         B <= b;
         count <= 6'd32;
         running <= 1;
      end
      else if (count == 0) begin
         running <=0;
         if(R<0) begin
            R <= R + B;
         end
         else begin
            R <= R - B;
         end
      end
      if (running) begin
         if (R<0) begin
            R <= R<<1;
            R[0] <= AQ[32];
            AQ <= AQ<<1;
         end
         if(R<0) begin 
            AQ[0] <= 0;
            R <= R + B;
            count <= count -6'd1;
         end
         else begin
            AQ[0] <= 1;
            R <= R - B;
            count <= count - 6'd1;
         end
      end
      else begin
         R <= R<<1;
         R[0] <= AQ[32];
         AQ <= AQ<<1;
      end
      if(R<0) begin 
         AQ[0] <= 0;
         R <= R + B;
         count <= count -6'd1;
      end
      else begin
         AQ[0] <= 1;
         R <= R - B;
         count <= count - 6'd1;
      end                
   end