signal-processing - 在 Chisel 中构建 DspComplex ROM

Question

我正在尝试使用 DSPComplex 和 FixedPoint 类型构建基于 ROM 的窗口函数，但似乎一直遇到以下错误:

chisel3.core.Binding$ExpectedHardwareException: vec element 'dsptools.numbers.DspComplex@32' must be hardware, not a bare Chisel type

我尝试这样做的源代码如下所示:

class TaylorWindow(len: Int, window: Seq[FixedPoint]) extends Module {
    val io = IO(new Bundle {
        val d_valid_in = Input(Bool()) 
        val sample = Input(DspComplex(FixedPoint(16.W, 8.BP), FixedPoint(16.W, 8.BP)))
        val windowed_sample = Output(DspComplex(FixedPoint(24.W, 8.BP), FixedPoint(24.W, 8.BP)))
        val d_valid_out = Output(Bool()) 
    })
     val win_coeff = Vec(window.map(x=>DspComplex(x, FixedPoint(0, 16.W, 8.BP))).toSeq) // ROM storing our coefficients. 

    io.d_valid_out := io.d_valid_in
    val counter = Reg(UInt(10.W))

    // Implicit reset
    io.windowed_sample:= io.sample * win_coeff(counter)
    when(io.d_valid_in) {
        counter := counter + 1.U
    }
}
println(getVerilog(new TaylorWindow(1024, fp_seq)))

我实际上是从一个文件中读取系数(这个特定窗口有一个复杂的生成函数，我在其他地方用 Python 做的)

val filename = "../generated/taylor_coeffs"
val coeff_file = Source.fromFile(filename).getLines
val double_coeffs = coeff_file.map(x => x.toDouble)
val fp_coeffs = double_coeffs.map(x => FixedPoint.fromDouble(x, 16.W, 8.BP))
val fp_seq = fp_coeffs.toSeq

这是否意味着 DSPComplex 类型无法转换为 Verilog？注释掉 win_coeff 行似乎使整个事情生成(但显然没有做我想要它做的事情)

Answer 1

我认为你应该尝试使用

  val win_coeff = VecInit(window.map(x=>DspComplex.wire(x, FixedPoint.fromDouble(0.0, 16.W, 8.BP))).toSeq) // ROM storing our coefficients.

这将创建您想要的硬件值。 Vec 只是创建一个指定类型的 Vec