case - Verilog case 语句中匹配的多个项目

Question

我有一个状态机，其中有几个非常相似的状态。我可以为每个状态编写它，如下例所示:

module CHECK_FSM (
GO,
DONE,
CLK, RESETN );

input       GO;
output reg  DONE;
input       CLK,RESETN;

reg[7:0]    state;

reg[7:0]    next_state; 

    //the actual registers
    always @(posedge CLK or negedge RESETN)
        if (!RESETN)    state <= 8'd0;
        else            state <= next_state;

    //next state logic
    always @(*)
        begin
        //defaults
        next_state = state;
        DONE = 1'b0; //low by default

        case(state)
            0: //S_INIT
                if(GO==1'b1)
                    next_state = 8'd1;
                else
                    next_state = 8'd0;
            1: //S_WAIT_1:
                if(GO==1'b1)
                    next_state = state+1; //continue
                else
                    next_state = 8'd0; //go back to S_INIT
            2: //S_WAIT_2:
                if(GO==1'b1)
                    next_state = state+1; //continue
                else
                    next_state = 8'd0; //go back to S_INIT
            3: //S_WAIT_3:
                if(GO==1'b1)
                    next_state = state+1; //continue
                else
                    next_state = 8'd0; //go back to S_INIT
            //...
            127: //S_FINISH
                begin
                DONE = 1'b1;
                next_state = state; //stay put
                end

            default: next_state= 8'd0;
            endcase
        end

endmodule

我想知道是否有办法指定 case多个状态的声明。就像是:

        case(state)
            0: //S_INIT
                if(GO==1'b1)
                    next_state = 8'd1;
                else
                    next_state = 8'd0;
            [1-->126]:
                if(GO==1'b1)
                    next_state = state+1; //continue
                else
                    next_state = 8'd0; //go back to S_INIT
            127: //S_FINISH
                begin
                DONE = 1'b1;
                next_state = state; //stay put
                end

            default: next_state= 8'd0;
            endcase

我想避免重复语句(都是相同的)，以便更清楚，并避免在之后需要修改时出错(我的实际 FSM 比这更复杂......)。有任何想法吗 ？
PS:代码是用来合成的。就我而言，综合工具不支持 SystemVerilog 语句，所以我希望有一个 Verilog 解决方案。

Answer 1

case inside SystemVerilog 中的语句将完全符合您的要求。但是由于您已经限制自己使用 Verilog，使用 if/else 可能更实用。链而不是给定示例的 case 语句

if (state==0) begin : S_INIT
                if(GO==1'b1)
                    next_state = 8'd1;
                else
                    next_state = 8'd0;
              end
 else if (state >0 && state < 127) begin
                if(GO==1'b1)
                    next_state = state+1; //continue
                else
                    next_state = 8'd0; //go back to S_INIT
            end
else if (state == 127) begin : S_FINISH
                DONE = 1'b1;
                next_state = state; //stay put
                end
else begin : S_DEFUALT
            default: next_state= 8'd0;
end

或者你仍然可以使用这种形式的 case 语句

case(1)
  state==0: //S_INIT
                if(GO==1'b1)
                    next_state = 8'd1;
                else
                    next_state = 8'd0;
  (state>0&&state<127):
                if(GO==1'b1)
                    next_state = state+1; //continue
                else
                    next_state = 8'd0; //go back to S_INIT
  state==127: //S_FINISH
                begin
                DONE = 1'b1;
                next_state = state; //stay put
                end
  default: next_state= 8'd0;
endcase