mips - 什么是 MIPS 首字母缩略词中的 "interlocked pipeline"？

Question

我正在使用 MIPS 处理器架构。

根据本教程，它指出:没有互锁管道阶段的微处理器
http://en.wikipedia.org/wiki/MIPS_architecture

One major barrier to pipelining was that some instructions, like division, take longer to complete and the CPU therefore has to wait before passing the next instruction into the pipeline.
One solution to this problem is to use a series of interlocks that allows stages to indicate that they are busy, pausing the other stages upstream.
Hennessy's team viewed these interlocks as a major performance barrier since they had to communicate to all the modules in the CPU which takes time, and appeared to limit the clock speed.
A major aspect of the MIPS design was to fit every sub-phase, including cache-access, of all instructions into one cycle, thereby removing any needs for interlocking, and permitting a single cycle throughput.

这个链接说:---
https://www.cs.tcd.ie/Jeremy.Jones/vivio/dlx/dlxtutorial.htm

issue a "stall" instruction instead of a nop instruction upon a stall

Interlock Pipeline 的缺点究竟是什么？
为什么路由器更喜欢采用 MIPS 架构的处理器？

Answer 1

A major aspect of the MIPS design was to fit every sub-phase, including cache-access, of all instructions into one cycle, thereby removing any needs for interlocking, and permitting a single cycle throughput.

但是在更高版本的 MIPS 中， http://cs.nyu.edu/courses/spring02/V22.0480-002/vliw.pdf幻灯片 9，互锁被重新引入架构:

• After all MIPS originally stood for something like Microprocessor without interlocking pipeline stages
• Because new implementations (with different memory latencies) would have required more than one slot and we don’t like correctness of code being dependent on the version of the implementation.
• Because other instructions required interlocking anyway (e.g. floating-point)
• Because it is not that painful to do interlocking

所以，考虑你的问题:

What exactly is Interlock Pipeline disadvantage ?

互锁需要更复杂的硬件(CPU的控制单元)，这在手绘晶体管和10万个晶体管的CPU时代并不是那么容易设计和测试的。他们选择了设计无互锁的 CPU 内核的目标，但他们失败了。他们无法在没有互锁的情况下生产兼容系列的商用芯片。

Why routers use to prefer Processors with MIPS Architecture ?

从历史上看，它们在第一个网络设备中很受欢迎，并且可能由于惯性和对基于 MIPS 的设备(来自网络设备制造商和 MIPS 芯片制造商)的投资而在下一个设备中使用。

查看 Dominic Sweetman 所著的“See MIPS Run”一书，第 15、16、22 页
http://books.google.com/books?id=kk8G2gK4Tw8C&pg=PR15

在 1990 年代中期，有几种易于使用的 MIPS 芯片，R4600、RM5200 和 RM7000。 1993 年的 R4600 被 Cisco 使用，下一个型号具有 64 位总线和大型片上 L2 缓存。他们有足够的性能来驱动当时的路由器。

在2010年代，我认为ARM上有路由器(现在有很多 SoCs with network and ARM)。这是因为 ARM 是最广泛授权的架构(就授权核数而言， 78% in 2011)；第二种架构是 ARC 占 10%(检查您的 PC 或笔记本电脑上的 Intel vPro 标签 - 如果您有标签，则说明您的芯片组中有 ARC 内核；它们也用于许多 SSD Controller )。 MIPS 在该评级中仅排名第三，仅占市场 100 亿个内核总数的 6%。