memory-barriers - 内存屏障 : a Hardware View for Software Hackers Example 3

Question

我正在从原始论文中复制该图的文本，Memory Barriers: a Hardware View for Software Hackers .

Table 4 shows three code fragments, executed concurrently by CPUs 0, 1, and 2. All variables are initially zero.

Note that neither CPU 1 nor CPU 2 can proceed to line 5 until they see CPU 0’s assignment to “b” on line 3. Once CPU 1 and 2 have executed their memory barriers on line 4, they are both guaranteed to see all assignments by CPU 0 preceding its memory barrier on line 2. Similarly, CPU 0’s memory barrier on line 8 pairs with those of CPUs 1 and 2 on line 4, so that CPU 0 will not execute the assignment to “e” on line 9 until after its assignment to “a” is visible to both of the other CPUs. Therefore, CPU 2’s assertion on line 9 is guaranteed not to fire.

对我来说，CPU0 上的第 6-9 行似乎完全没有必要，因为 CPU 0 的第 2 行的内存屏障和 CPU 1&2 的第 4 行的内存屏障保证了 b=1 的效果。已取货，以及之前的所有商店，又名 a=1 .然后，断言 e == 0 || a == 1总是成功。
我不知道我是否忽略了什么。任何澄清表示赞赏。

Answer 1

将第 6-9 行排除在 CPU 0 之外肯定会阻止 assert() 触发。再说一次，鉴于 e，删除断言以外的所有代码也是如此。初始化为零。但是，这两种修改都无济于事。相反，断言的关键点是“CPU 2 是否有可能在其执行结束时看到状态 e==1&&a==0？”以这种方式看待它应该迫使您思考什么值以什么顺序传播到哪里。

但是你忽略的主要事情是这篇论文非常古老，从那时起，在理解和形式化内存排序方面取得了巨大的进步。我正在向 Is Parallel Programming Hard, And, If So, What Can You Do About It? 添加新的内存排序章节同时，一对LWN文章here和 here可能会有所帮助。

或者，如果您想查看本书的当前状态，git clone git://git.kernel.org/pub/scm/linux/kernel/git/paulmck/perfbook.git .