VHDL TG68 核心 data_in 和 data_out 到 datainout

Question

我想用tg68内核但是有问题。当我在 Altera Quartus 中编译我的设计时，它给了我 16 data_in和 16 data_out信号，我需要将它们加入 inout针脚。

这是我用 VHDL 编写的一些代码，需要有人可以检查我的代码，因为我认为该代码没问题。这是顶层设计文件的代码，需要生成inout来自 data_in 的别针和 data_out来自 tg68.vhd 文件的信号。它还需要在最终设计中使用来自 tg68.vhd 的所有信号。 (信号如 as 、 uds 、 lds ...)

这是代码:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity datainout is
    port(
    clk          : in std_logic;
    reset        : in std_logic;
        clkena_in    : in std_logic:='1';

        IPL          : in std_logic_vector(2 downto 0):="111";
        dtack        : in std_logic;
        addr          : out std_logic_vector(31 downto 0);

        as            : buffer std_logic;
        uds          : buffer std_logic;
        lds          : buffer std_logic;
        rw            : buffer std_logic;
        drive_data    : out std_logic;
        datainout : inout std_logic_vector(15 downto 0)         
        );
end datainout;

ARCHITECTURE logic OF datainout IS

    COMPONENT TG68
    PORT (
      clk          : in std_logic;
    reset        : in std_logic;
        clkena_in    : in std_logic;
        data_in      : in std_logic_vector(15 downto 0);
        IPL          : in std_logic_vector(2 downto 0);
        dtack        : in std_logic;
        addr          : out std_logic_vector(31 downto 0);
        data_out      : out std_logic_vector(15 downto 0);
        as            : out std_logic;
        uds          : out std_logic;
        lds          : out std_logic;
        rw            : out std_logic;
        drive_data    : out std_logic
        );
    END COMPONENT;

signal data_in : STD_LOGIC_VECTOR (15 downto 0);
signal data_out : STD_LOGIC_VECTOR (15 downto 0);

BEGIN

data_in <= datainout;
TG68_inst: TG68
    PORT MAP (
        data_in => data_in,
    data_out => data_out,
    clk => clk,
    reset => reset,
    clkena_in => clkena_in,
    IPL => IPL,
    dtack => dtack,
    addr => addr,
    as => as,
    rw => rw,
    uds => uds,
    lds => lds,
        drive_data => drive_data   
        );

datainout(15 downto 8) <= data_out(15 downto 8) when as = '0' and rw = '0' and uds='0' else "ZZZZZZZZ";
datainout(7 downto 0) <= data_out(7 downto 0) when as = '0' and rw = '0' and lds='0' else "ZZZZZZZZ";
END;   

Answer 1

基本做法inout信号是:

data_in   <= data_pins;
data_pins <= data_out when enable = '1' else (others => 'Z');

据我所知，这正是您所做的，但数据总线分为两半。假设这就是你的意图，那很好!