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我正在尝试使用 VHDL 中的精简指令集对控制单元进行建模。我一直在编译很多以确保代码仍然可以编译，但是在某个地方，我一定做错了什么。在充实了许多指令的解码状态后，我开始遇到以下一组错误。
Error (10500): VHDL syntax error at controlunit.vhd(164) near text "when"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement
Error (10500): VHDL syntax error at controlunit.vhd(176) near text "when"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement
Error (10500): VHDL syntax error at controlunit.vhd(183) near text "when"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement
Error (10500): VHDL syntax error at controlunit.vhd(190) near text "case"; expecting "if"
Error (10500): VHDL syntax error at controlunit.vhd(195) near text "Begin"; expecting ":=", or "<="
Error (10500): VHDL syntax error at controlunit.vhd(203) near text "process"; expecting "if"
Error (10500): VHDL syntax error at controlunit.vhd(204) near text "behavior"; expecting "if"
通常情况下，这些类型的错误完全在我修复的能力范围内，但我已经多次检查我的代码，据我所知，所有流程 block 和案例语句都已正确定义。
我担心，由于我对 VHDL 相当陌生，我可能会遗漏一些我自己从未发现的语法细节。任何 VHDL 专家都可以帮助我隔离代码中的问题吗？谢谢!
您可以在下面的代码块中找到我的代码。
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity ControlUnit is
port(
clk: IN std_logic;
Mem_rd: OUT std_logic :='1'; --signal to read from RAM/ROM
Mem_wr: OUT std_logic :='1'; --signal to write RAM
Mem_cs: OUT std_logic :='1'; --signal to select either RAM or ROM
Z: IN std_logic; --zero signal from ALU
N: IN std_logic; --negative signal from ALU
R_we: OUT std_logic; --read/write enable signal to register file
ld_op: OUT std_logic; --bus control signal for memory load operations
st_op: OUT std_logic; --bus control signal for memory read operations
ctl_wd: OUT std_logic_vector(14 downto 0); --processor control word
const_out: OUT std_logic_vector(15 downto 0); --constant value from instruction
CU_addr_bus: INOUT std_logic_vector(15 downto 0); --processor address bus connection
CU_data_bus: INOUT std_logic_vector(15 downto 0); --processor data bus connection
run: IN std_logic; --signal allowing processor to execute its program
rst: IN std_logic --system reset signal
);
end ControlUnit;
architecture Behavior of ControlUnit is
-- Control Unit states for multi-cycle instruction execution
type states is (Reset, Fetch, Decode, Execute, WB);
signal CurrState, NextState : states;
-- Instruction set types
type ops is (nop, subx, orx, jmp, addx, andx, notx, srlx, sllx, ld, st, hlt, ret, addi, ba, bn, bz, sethi, call);
signal CurrOp, NextOp : ops;
-- Internal signal declarations
signal CurrPC, CurrSP, CurrIR, CurrDisp : std_logic_vector(15 downto 0);
signal NextPC, NextSP, NextIR, NextDisp : std_logic_vector(15 downto 0);
signal PCaEN, SPEN, PCdEN : std_logic;
signal currStatus, nextStatus : std_logic_vector(1 downto 0); --N & Z
begin
-- tri-state enables:
addr_bus <= CurrPC when PCaEN='1' else
CurrSP when SPEN='1' else
(others=>'Z');
data_bus <= CurrPC when PCdEN='1' else
(others => 'Z');
CombLogic : process(CurrState, run, CurrPC, CurrSP, CurrIR, CurrOp, data_bus)
begin
case CurrState is
when Reset => -------------------------RESET-------------------------
NextPC <= x"0080"; NextSP <= x"04FE";
NextIR <= x"0000"; NextOp <= nop;
NextStatus <= "00"; NextDisp <= x"0000";
PCaEN <= '1'; SPEN <= '0'; PCdEN <= '0'; -- setup fetch
mem_cs <= '0'; mem_rd <= '0'; mem_wr <= '1'; -- active low; setup fetch
if run = '0' then NextState <= Reset; -- active low run
else NextState <= Fetch;
end if;
when Fetch => -------------------------FETCH-------------------------
NextPC <= currPC; NextSP <= currSP;
NextIR <= data_bus; NextOp <= currOP;
PCaEN <= '1'; SPEN <= '0'; PCdEN <= '0';
mem_cs <= '0'; mem_rd <= '0'; mem_wr <= '1'; -- active low
R_we <= '0'; ctl_wd <= (others => '0'); const_out <= x"FFFF";
NextState <= Decode;
when Decode => ------------------------DECODE-------------------------
--fill in decode logic
if currIR(15) = '1' then NextOp <= call;
NextPC <= CurrPC+1; NextSP <= CurrSP; NextIR <= CurrIR; nextStatus <= currStatus; nextDisp <= currDisp;
PCaEN <= '0'; SPEN <= '0'; PCdEN <= '0'; -- store CurrPC to M[SP]
mem_cs <= '1'; mem_rd <= '1'; mem_wr <= '1';
R_we <= '0'; ctl_wd <= "0000"; const_out <= x"0000";
else if currIR(14) = '1' then
case currOP(10 downto 8) is
when "000" => NextOP <= hlt; --set signals for hlt
when "001" => NextOP <= ret; --set signals for ret
when "011" => NextOP <= addi; --set signals for addi
when "100" => NextOP <= ba; --set signals for ba
when "101" => NextOP <= bn; --set signals for bn
when "110" => NextOP <= bz; --set signals for bz
when "111" => NextOP <= sethi; --set signals for sethi
end case;
else
case currOP(10 downto 7) is
when "1010" => NextOP <= nop; --set signals for nop
NextPC <= CurrPC; NextSP <= CurrSP; NextIR <= CurrIR; nextStatus <= currStatus; nextDisp <= currDisp;
PCaEN <= '0'; SPEN <= '0'; PCdEN <= '0';
mem_cs <= '1'; mem_rd <= '1'; mem_wr <= '1';
R_we <= '0'; ctl_wd <= x"0000"; const_out <= x"0000";
when "1001" => NextOP <= subx; --set signals for subx
NextPC <= CurrPC; NextSP <= CurrSP; NextIR <= CurrIR; nextStatus <= currStatus; nextDisp <= currDisp;
PCaEN <= '0'; SPEN <= '0'; PCdEN <= '0';
mem_cs <= '1'; mem_rd <= '1'; mem_wr <= '1';
R_we <= '1'; ctl_wd <= currOP(14 downto 0)&'0'; const_out <= x"0000";
when "1000" => NextOP <= orx; --set signals for orx
NextPC <= CurrPC; NextSP <= CurrSP; NextIR <= CurrIR; nextStatus <= currStatus; nextDisp <= currDisp;
PCaEN <= '0'; SPEN <= '0'; PCdEN <= '0';
mem_cs <= '1'; mem_rd <= '1'; mem_wr <= '1';
R_we <= '1'; ctl_wd <= currOP(14 downto 0)&'0'; const_out <= x"0000";
when "0111" => NextOP <= jmp; --set signals for jmp
NextPC <= CurrPCL; NextSP <= CurrSP; NextIR <= CurrIR; nextStatus <= currStatus; nextDisp <= currDisp;
PCaEN <= '0'; SPEN <= '0'; PCdEN <= '0';
mem_cs <= '1'; mem_rd <= '1'; mem_wr <= '1';
R_we <= '0'; ctl_wd <= currOP(14 downto 0)&'0'; const_out <= x"0000";
when "0110" => NextOP <= addx; --set signals for addx
NextPC <= CurrPC; NextSP <= CurrSP; NextIR <= CurrIR; nextStatus <= currStatus; nextDisp <= currDisp;
PCaEN <= '0'; SPEN <= '0'; PCdEN <= '0';
mem_cs <= '1'; mem_rd <= '1'; mem_wr <= '1';
R_we <= '1'; ctl_wd <= currOP(14 downto 0)&'0'; const_out <= x"0000";
when "0101" => NextOP <= andx; --set signals for andx
NextPC <= CurrPC; NextSP <= CurrSP; NextIR <= CurrIR; nextStatus <= currStatus; nextDisp <= currDisp;
PCaEN <= '0'; SPEN <= '0'; PCdEN <= '0';
mem_cs <= '1'; mem_rd <= '1'; mem_wr <= '1';
R_we <= '1'; ctl_wd <= currOP(14 downto 0)&'0'; const_out <= x"0000";
when "0100" => NextOP <= notx; --set signals for notx
NextPC <= CurrPC; NextSP <= CurrSP; NextIR <= CurrIR; nextStatus <= currStatus; nextDisp <= currDisp;
PCaEN <= '0'; SPEN <= '0'; PCdEN <= '0';
mem_cs <= '1'; mem_rd <= '1'; mem_wr <= '1';
R_we <= '1'; ctl_wd <= currOP(14 downto 0)&'0'; const_out <= x"0000";
when "0011" => NextOP <= srlx; --set signals for srlx
NextPC <= CurrPC; NextSP <= CurrSP; NextIR <= CurrIR; nextStatus <= currStatus; nextDisp <= currDisp;
PCaEN <= '0'; SPEN <= '0'; PCdEN <= '0';
mem_cs <= '1'; mem_rd <= '1'; mem_wr <= '1';
R_we <= '1'; ctl_wd <= currOP(14 downto 0)&'0'; const_out <= x"0000";
when "0010" => NextOP <= sllx; --set signals for sllx
NextPC <= CurrPC; NextSP <= CurrSP; NextIR <= CurrIR; nextStatus <= currStatus; nextDisp <= currDisp;
PCaEN <= '0'; SPEN <= '0'; PCdEN <= '0';
mem_cs <= '1'; mem_rd <= '1'; mem_wr <= '1';
R_we <= '1'; ctl_wd <= currOP(14 downto 0)&'0'; const_out <= x"0000";
when "0001" => NextOP <= ld; --set signals for ld
NextPC <= CurrPC; NextSP <= CurrSP; NextIR <= CurrIR; nextStatus <= currStatus; nextDisp <= currDisp;
PCaEN <= '0'; SPEN <= '0'; PCdEN <= '0';
mem_cs <= '0'; mem_rd <= '0'; mem_wr <= '1';
R_we <= '1'; ctl_wd <= currOP(14 downto 0)&'0'; const_out <= x"0000";
when "0000" => NextOP <= st; --set signals for st
NextPC <= CurrPC; NextSP <= CurrSP; NextIR <= CurrIR; nextStatus <= currStatus; nextDisp <= currDisp;
PCaEN <= '0'; SPEN <= '0'; PCdEN <= '0';
mem_cs <= '0'; mem_rd <= '1'; mem_wr <= '0';
R_we <= '0'; ctl_wd <= currOP(14 downto 0)&'0'; const_out <= x"0000";
end case;
end if;
NextState <= Execute;
when Execute => -------------------------EXECUTE-------------------------
case CurrOp is
when call => --call
NextPC <= CurrPC+1; NextSP <= CurrSP; NextIR <= CurrIR; nextStatus <= currStatus; nextDisp <= currDisp;
PCaEN <= '0'; SPEN <= '1'; PCdEN <= '1'; -- store CurrPC to M[SP]
mem_cs <= '0'; mem_rd <= '1'; mem_wr <= '0';
R_we <= '0'; ctl_wd <= "0000"; const_out <= x"0000";
--for bn and bz, execution of operation is dependent on signals N and Z
when others => null;
end case;
NextState <= WB;
when WB => -------------------------WB-------------------------
NextPC <= '0'&currIR(6 downto 0); NextSP <= CurrSP - 1; NextIR <= CurrIR; NextOp <= CurrOp;
PCaEN <= '0'; SPEN <= '0'; PCdEN <= '0'; -- setup fetch
mem_cs <= '1'; mem_rd <= '1'; mem_wr <= '1'; -- active low; setup fetch
R_we <= '0'; ctl_wd <= "0000"; const_out <= x"0000";
NextState <= Fetch;
when others => -------------------------OTHERS-------------------------
-- Should never be in this state!
NextPC <= x"00"; NextSP <= x"00"; NextIR <= x"00"; NextOp <= call;
PCaEN <= '0'; SPEN <= '0'; PCdEN <= '0';
mem_cs <= '1'; mem_rd <= '1'; mem_wr <= '1'; -- active low
R_we <= '0'; ctl_wd <= "00"; const_out <= x"FF";
NextState <= Reset;
end case;
end process;
-- Sequential Logic (asynchronous reset; registers update at positive-edge clock)
Regs : process(clk,rst)
Begin
if rst = '0' then CurrState <= Reset; -- Active Low Reset
CurrOp <= sethi; CurrPC <= x"80"; CurrSP <= x"FF"; CurrIR <= (others=>'0');
CurrStatus <= "00";
elsif (rising_edge(clk)) then CurrState <= NextState;
CurrOp <= NextOp; CurrPC <= NextPC; CurrSP <= NextSP; CurrIR <= NextIR;
CurrStatus <= NextStatus;
end if;
end process Regs;
end behavior;
最佳答案
-- Instruction set types
type ops is (nop, subx, orx, jmp, addx, andx, notx, srlx, sllx, ld, st, hlt, ret, addi, ba, bn, bz, sethi, call);
signal CurrOp, NextOp : ops;
例如 CurrOp 是一个枚举类型，其值显示为 ops 枚举。然而你有 CurrOp 的片段:
case currOP(10 downto 8) is
case currOP(10 downto 7) is
你的 case 语句的 when 表达式是字符串文字，长度分别为 3 或 4。
因此 CurrOp 不是数组类型，您不能将其切片并将其与字符串进行比较。
为什么分析会走到这一步是因为没有告诉您这很有趣。与信号分配的目标不同，表达式在详细说明时而不是分析时进行评估:
library ieee;
use ieee.std_logic_1164.all;
entity foo is
end entity;
architecture fum of foo is
-- Instruction set types
type ops is (nop, subx, orx, jmp, addx, andx, notx, srlx, sllx, ld, st, hlt, ret, addi, ba, bn, bz, sethi, call);
signal CurrOp, NextOp: ops;
begin
CurrOp(10 downto 7) <= "1001";
NextOp(10 downto 8) <= "011";
end architecture;
ghdl -a foo.vhdl foo.vhdl:13:11: type of prefix is not an array
foo.vhdl:14:11: type of prefix is not an array
ghdl: compilation error
(-a是ghdl分析命令)
实际上，一个选择只能是一个 ops 枚举值。为了让它更可口，您可以选择:
choices ::= choice { | choice }
您还可以为所有保证在 case 语句之前的选择中分配的信号分配默认值，然后仅分配那些在每个 case 语句备选方案中具有不同值的信号。在同一个模拟增量中，只会安排最后一个分配(只有一个 future 事件)。
除了大量错误外，阻止进一步分析的主要因素是 else if 和 `else 是合适的。
在排除故障时发现了很多或错误，您希望将这些与文件中的相同语法位置进行比较:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- use IEEE.STD_LOGIC_UNSIGNED.all;
use ieee.numeric_std.all;
entity ControlUnit is
port(
clk: IN std_logic;
Mem_rd: OUT std_logic :='1'; --signal to read from RAM/ROM
Mem_wr: OUT std_logic :='1'; --signal to write RAM
Mem_cs: OUT std_logic :='1'; --signal to select either RAM or ROM
Z: IN std_logic; --zero signal from ALU
N: IN std_logic; --negative signal from ALU
R_we: OUT std_logic; --read/write enable signal to register file
ld_op: OUT std_logic; --bus control signal for memory load operations
st_op: OUT std_logic; --bus control signal for memory read operations
ctl_wd: OUT std_logic_vector(14 downto 0); --processor control word
const_out: OUT std_logic_vector(15 downto 0); --constant value from instruction
CU_addr_bus: INOUT std_logic_vector(15 downto 0); --processor address bus connection
CU_data_bus: INOUT std_logic_vector(15 downto 0); --processor data bus connection
run: IN std_logic; --signal allowing processor to execute its program
rst: IN std_logic --system reset signal
);
end ControlUnit;
architecture Behavior of ControlUnit is
-- Control Unit states for multi-cycle instruction execution
type states is (Reset, Fetch, Decode, Execute, WB);
signal CurrState, NextState : states;
-- Instruction set types
type ops is (nop, subx, orx, jmp, addx, andx, notx, srlx, sllx, ld, st, hlt, ret, addi, ba, bn, bz, sethi, call);
signal CurrOp, NextOp : ops;
-- Internal signal declarations
signal CurrPC, CurrSP, CurrIR, CurrDisp : std_logic_vector(15 downto 0);
signal NextPC, NextSP, NextIR, NextDisp : std_logic_vector(15 downto 0);
signal PCaEN, SPEN, PCdEN : std_logic;
signal currStatus, nextStatus : std_logic_vector(1 downto 0); --N & Z
begin
-- tri-state enables:
CU_addr_bus <= CurrPC when PCaEN='1' else
CurrSP when SPEN='1' else
(others=>'Z');
CU_data_bus <= CurrPC when PCdEN='1' else
(others => 'Z');
CombLogic : process(CurrState, run, CurrPC, CurrSP, CurrIR, CurrOp, CU_data_bus)
begin
case CurrState is
when Reset => -------------------------RESET-------------------------
NextPC <= x"0080";
NextSP <= x"04FE";
NextIR <= x"0000";
NextOp <= nop;
NextStatus <= "00";
NextDisp <= x"0000";
PCaEN <= '1';
SPEN <= '0';
PCdEN <= '0'; -- setup fetch
mem_cs <= '0';
mem_rd <= '0';
mem_wr <= '1'; -- active low; setup fetch
if run = '0' then NextState <= Reset; -- active low run
else NextState <= Fetch;
end if;
when Fetch => -------------------------FETCH-------------------------
NextPC <= currPC;
NextSP <= currSP;
NextIR <= CU_data_bus;
NextOp <= currOP;
PCaEN <= '1';
SPEN <= '0';
PCdEN <= '0';
mem_cs <= '0';
mem_rd <= '0';
mem_wr <= '1'; -- active low
R_we <= '0';
ctl_wd <= (others => '0');
const_out <= x"FFFF";
NextState <= Decode;
when Decode => ------------------------DECODE-------------------------
--fill in decode logic
if currIR(15) = '1' then
NextOp <= call;
NextPC <= std_logic_vector (unsigned(CurrPC) + 1);
NextSP <= CurrSP;
NextIR <= CurrIR;
nextStatus <= currStatus;
nextDisp <= currDisp;
PCaEN <= '0';
SPEN <= '0';
PCdEN <= '0'; -- store CurrPC to M[SP]
mem_cs <= '1';
mem_rd <= '1';
mem_wr <= '1';
R_we <= '0';
ctl_wd <= (others => '0');
const_out <= x"0000";
elsif currIR(14) = '1' then
case currIR(10 downto 8) is
when "000" => NextOP <= hlt; --set signals for hlt
when "001" => NextOP <= ret; --set signals for ret
when "011" => NextOP <= addi; --set signals for addi
when "100" => NextOP <= ba; --set signals for ba
when "101" => NextOP <= bn; --set signals for bn
when "110" => NextOP <= bz; --set signals for bz
when "111" => NextOP <= sethi; --set signals for sethi
when others => NextOp <= nop;
end case;
else
case currIR(10 downto 7) is
when "1010" =>
NextOP <= nop; --set signals for nop
NextPC <= CurrPC;
NextSP <= CurrSP;
NextIR <= CurrIR;
nextStatus <= currStatus;
nextDisp <= currDisp;
PCaEN <= '0';
SPEN <= '0';
PCdEN <= '0';
mem_cs <= '1';
mem_rd <= '1';
mem_wr <= '1';
R_we <= '0';
ctl_wd <= (others => '0');
const_out <= x"0000";
when "1001" =>
NextOP <= subx; --set signals for subx
NextPC <= CurrPC;
NextSP <= CurrSP;
NextIR <= CurrIR;
nextStatus <= currStatus;
nextDisp <= currDisp;
PCaEN <= '0';
SPEN <= '0';
PCdEN <= '0';
mem_cs <= '1';
mem_rd <= '1';
mem_wr <= '1';
R_we <= '1';
ctl_wd <= currIR(14 downto 0) & '0';
const_out <= x"0000";
when "1000" =>
NextOP <= orx; --set signals for orx
NextPC <= CurrPC;
NextSP <= CurrSP;
NextIR <= CurrIR;
nextStatus <= currStatus;
nextDisp <= currDisp;
PCaEN <= '0';
SPEN <= '0';
PCdEN <= '0';
mem_cs <= '1';
mem_rd <= '1';
mem_wr <= '1';
R_we <= '1';
ctl_wd <= currIR(14 downto 0) & '0';
const_out <= x"0000";
when "0111" =>
NextOP <= jmp; --set signals for jmp
NextPC <= CurrPC;
NextSP <= CurrSP;
NextIR <= CurrIR;
nextStatus <= currStatus;
nextDisp <= currDisp;
PCaEN <= '0';
SPEN <= '0';
PCdEN <= '0';
mem_cs <= '1';
mem_rd <= '1';
mem_wr <= '1';
R_we <= '0';
ctl_wd <= currIR(14 downto 0) & '0';
const_out <= x"0000";
when "0110" =>
NextOP <= addx; --set signals for addx
NextPC <= CurrPC;
NextSP <= CurrSP;
NextIR <= CurrIR;
nextStatus <= currStatus;
nextDisp <= currDisp;
PCaEN <= '0';
SPEN <= '0';
PCdEN <= '0';
mem_cs <= '1';
mem_rd <= '1';
mem_wr <= '1';
R_we <= '1';
ctl_wd <= currIR(14 downto 0) & '0';
const_out <= x"0000";
when "0101" =>
NextOP <= andx; --set signals for andx
NextPC <= CurrPC;
NextSP <= CurrSP;
NextIR <= CurrIR;
nextStatus <= currStatus;
nextDisp <= currDisp;
PCaEN <= '0';
SPEN <= '0';
PCdEN <= '0';
mem_cs <= '1';
mem_rd <= '1';
mem_wr <= '1';
R_we <= '1';
ctl_wd <= currIR(14 downto 0) & '0';
const_out <= x"0000";
when "0100" =>
NextOP <= notx; --set signals for notx
NextPC <= CurrPC;
NextSP <= CurrSP;
NextIR <= CurrIR;
nextStatus <= currStatus;
nextDisp <= currDisp;
PCaEN <= '0';
SPEN <= '0';
PCdEN <= '0';
mem_cs <= '1';
mem_rd <= '1';
mem_wr <= '1';
R_we <= '1';
ctl_wd <= currIR(14 downto 0) & '0';
const_out <= x"0000";
when "0011" =>
NextOP <= srlx; --set signals for srlx
NextPC <= CurrPC;
NextSP <= CurrSP;
NextIR <= CurrIR;
nextStatus <= currStatus;
nextDisp <= currDisp;
PCaEN <= '0';
SPEN <= '0';
PCdEN <= '0';
mem_cs <= '1';
mem_rd <= '1';
mem_wr <= '1';
R_we <= '1';
ctl_wd <= currIR(14 downto 0) & '0';
const_out <= x"0000";
when "0010" =>
NextOP <= sllx; --set signals for sllx
NextPC <= CurrPC;
NextSP <= CurrSP;
NextIR <= CurrIR;
nextStatus <= currStatus;
nextDisp <= currDisp;
PCaEN <= '0';
SPEN <= '0';
PCdEN <= '0';
mem_cs <= '1';
mem_rd <= '1';
mem_wr <= '1';
R_we <= '1';
ctl_wd <= currIR(14 downto 0) & '0';
const_out <= x"0000";
when "0001" =>
NextOP <= ld; --set signals for ld
NextPC <= CurrPC;
NextSP <= CurrSP;
NextIR <= CurrIR;
nextStatus <= currStatus;
nextDisp <= currDisp;
PCaEN <= '0';
SPEN <= '0';
PCdEN <= '0';
mem_cs <= '0';
mem_rd <= '0';
mem_wr <= '1';
R_we <= '1';
ctl_wd <= currIR(14 downto 0)&'0';
const_out <= x"0000";
when "0000" =>
NextOP <= st; --set signals for st
NextPC <= CurrPC;
NextSP <= CurrSP;
NextIR <= CurrIR;
nextStatus <= currStatus;
nextDisp <= currDisp;
PCaEN <= '0';
SPEN <= '0';
PCdEN <= '0';
mem_cs <= '0';
mem_rd <= '1';
mem_wr <= '0';
R_we <= '0';
ctl_wd <= currIR(14 downto 0) & '0';
const_out <= x"0000";
when others =>
NextOP <= nop; --set signals for nop
NextPC <= CurrPC;
NextSP <= CurrSP;
NextIR <= CurrIR;
nextStatus <= currStatus;
nextDisp <= currDisp;
PCaEN <= '0';
SPEN <= '0';
PCdEN <= '0';
mem_cs <= '1';
mem_rd <= '1';
mem_wr <= '1';
R_we <= '0';
ctl_wd <= (others => '0');
const_out <= x"0000";
end case;
end if;
NextState <= Execute;
when Execute => -------------------------EXECUTE-------------------------
case CurrOp is
when call => --call
NextPC <= std_logic_vector( unsigned (CurrPC) + 1);
NextSP <= CurrSP;
NextIR <= CurrIR;
nextStatus <= currStatus;
nextDisp <= currDisp;
PCaEN <= '0';
SPEN <= '1';
PCdEN <= '1'; -- store CurrPC to M[SP]
mem_cs <= '0';
mem_rd <= '1';
mem_wr <= '0';
R_we <= '0';
ctl_wd <= (others => '0');
const_out <= x"0000";
--for bn and bz, execution of operation is dependent on signals N and Z
when others => null;
end case;
NextState <= WB;
when WB => -------------------------WB-------------------------
NextPC <= '0' & currIR(6 downto 0);
NextSP <= std_logic_vector(unsigned(CurrSP) - 1);
NextIR <= CurrIR;
NextOp <= CurrOp;
PCaEN <= '0';
SPEN <= '0';
PCdEN <= '0'; -- setup fetch
mem_cs <= '1';
mem_rd <= '1';
mem_wr <= '1'; -- active low; setup fetch
R_we <= '0';
ctl_wd <= (others => '0'); -- "0000";
const_out <= x"0000";
NextState <= Fetch;
-- when others => -------------------------OTHERS-------------------------
-- -- Should never be in this state!
-- NextPC <= x"00"; NextSP <= x"00"; NextIR <= x"00"; NextOp <= call;
-- PCaEN <= '0'; SPEN <= '0'; PCdEN <= '0';
-- mem_cs <= '1'; mem_rd <= '1'; mem_wr <= '1'; -- active low
-- R_we <= '0'; ctl_wd <= "00"; const_out <= x"FF";
-- NextState <= Reset;
end case;
end process;
-- Sequential Logic (asynchronous reset; registers update at positive-edge clock)
Regs : process(clk,rst)
Begin
if rst = '0' then CurrState <= Reset; -- Active Low Reset
CurrOp <= sethi;
CurrPC <= x"0080";
CurrSP <= x"FFFE";
CurrIR <= (others=>'0');
CurrStatus <= "00";
elsif (rising_edge(clk)) then CurrState <= NextState;
CurrOp <= NextOp;
CurrPC <= NextPC;
CurrSP <= NextSP;
CurrIR <= NextIR;
CurrStatus <= NextStatus;
end if;
end process Regs;
end behavior;
关于syntax-error - 带有 Case 语句和过程声明的 VHDL 中的语法错误，我们在Stack Overflow上找到一个类似的问题： https://stackoverflow.com/questions/22135112/
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