coding-style - 1、2 或 3 进程对 VHDL 中的 FSM 意味着什么？

Question

关于如何在 VHDL 中编写有限状态机 (FSM) 似乎存在一些争论。人们谈论 1-process、2-process 或 3-process FSM 就好像每个人都确切地知道它的含义以及每个过程的作用一样。然而，我一直无法找到一个准确的定义，而且存在的例子似乎是矛盾的。

这是一个客观的问题:每种 FSM 样式(1-process、2-process、3-process)在代码方面有什么区别？我知道有个人偏好的组成部分，但当然可以客观地回答这个问题并列出每种方法的优点。

谢谢，

Answer 1

据我所知，FSM 有 4 种类型。 Mealy、Moore、Medvedev 和注册输出。在注册输出中，您最多可以有 4 个进程(您可以找到示例 here )。在 Medvedev 中，可以有 1 或 2 个。在其他情况下，状态机可以有 1 或 2 个进程，并且可以与组合进程合并的输出进程有 1 个。

假设这个 FSM:




单进程 FSM VHDL 代码将是:

FSM_FF: process (CLK, RESET)
begin
    if RESET='1' then
        STATE <= START;
    elsif CLK'event and CLK='1' then
        case STATE is
        when START =>
            if X=GO_MID then
                STATE <= MIDDLE;
            end if;
        when MIDDLE =>
            if X=GO_STOP then
                STATE <= STOP;
            end if;
        when STOP =>
            if X=GO_START then
                STATE <= START;
            end if;
        when others => STATE <= START;
        end case;
    end if;
end process FSM_FF;

两进程 FSM VHDL代码:

FSM_LOGIC: process( STATE, X)
begin
    case STATE is
    when START =>
        if X=GO_MID then
            NEXT_STATE <= MIDDLE;
        end if ;
    when MIDDLE =>
        ...
    when others => NEXT_STATE <= START;
    end case;
end process FSM_LOGIC;
---------------------------------------------
FSM_FF: process(CLK, RESET)
begin
    if RESET='1' then
        STATE <= START;
    elsif CLK'event and CLK='1' then
        STATE <= NEXT_STATE;
    end if;
end process FSM_FF;

您应该使用哪一个？

根据 Jensen ,

It depends on a number of things. Do you need a Moore machine or a Mealy machine? Is the downstream logic that received the output signal synchronous or combinatorial? It also depends on which style of coding you prefer.

Saheb Zamani 教授从三个方面比较了 1-Process 和 2-Process ( slide 86):

• Structure and Readability: From the hardware perspective, combinational and sequential elements are two different things, so a separated design is closer to hardware. On the other side, the graphical FSM (without output equations) resembles more a 1 process than a 2 process description.
• Simulation: Error detection easier with two state processes due to access to intermediate signals.
• Synthesis: 2 state processes can lead to smaller generic netlist and therefore to better synthesis results (depends on synthesizer but in general, it is closer to hardware)

附言我找不到这些链接的原始来源，所以我只添加了我使用的来源。但是 this one更全面，还包括一些示例。