arrays - Modelsim VHDL 阵列初始化发出警告 (vcom-1320)

Question

我正在使用 Modelsim 的 VHDL 编译器 (vcom) 对 SublimeText (VHDL 2008) 进行代码检查。在初始化一组标准逻辑向量时，我收到以下警告:

vcom: warning Warning - (vcom-1320) Type of expression "(OTHERS => '0')" is ambiguous; using element type STD_LOGIC_VECTOR, not aggregate type t_a_reg.

一个最小的代码示例如下:

library ieee;
use ieee.std_logic_1164.all;

entity module is
  port
  (
    clk : in std_logic;
    rst : in std_logic;
    ...
  );
end entity;

architecture rtl of module is

  type t_a_reg is array (integer range <>) of std_logic_vector(15 downto 0);
  signal s_event_reg : t_a_reg(1 downto 0) := (others => (others => '0'));   -- this gives the warning

  ...

begin
  ...

end architecture;

我通过输入 verror 1320 来检查 Modelsim在 tcl 控制台中，它给出了以下解释:

vcom Message # 1320:The expression of each element association of an array aggregate can beof the element type or the type of the aggregate itself. When an arrayaggregate is of an array type whose element subtype is composite, it ispossible for certain kinds of its element association expressions to beinterpreted as being potentially either of these two types. This willnormally happen only if the ambiguous expression is itself an aggregate(because the type of an aggregate must be determined solely from thecontext in which the aggregate appears, excluding the aggregate itselfbut using the fact that the type of the aggregate shall be a compositetype) or a function call that identifies two overloaded functions.This ambiguity is resolved in favor of the element type to supportbackwards compatibility with prior versions of VHDL, in which theelement type was the only type considered.[DOC: IEEE Std 1076-2008 VHDL LRM - 9.3.3.3 Array aggregates]

我找到了两种方法来初始化数组而不会收到警告，但都存在缺陷。
第一个是有问题的，如果 std_logic_vector 的大小发生变化，因为我必须修改初始化:

  type t_a_reg is array (integer range <>) of std_logic_vector(15 downto 0);
  signal s_event_reg : t_a_reg(1 downto 0) := (others => x"0000");            -- no warning

第二种方法非常冗长，我不太喜欢它:

  subtype t_vec is std_logic_vector(15 downto 0);
  constant c_vec_init : t_vec := (others => '0');
  type t_a_reg is array (integer range <>) of std_logic_vector(15 downto 0);
  signal s_event_reg : t_a_reg(1 downto 0) := (others => c_vec_init);        -- no warning

问题是:是否有正确的 VHDL-2008 初始化数组的方法，所以我没有收到警告？这个问题更像是一个哲学问题，因为代码有效。我只是想知道，如果我遗漏了什么。
提前致谢!
彼得
编辑:
忘了说了，我也试过一个合格的表达:

  type t_a_reg is array (integer range <>) of std_logic_vector(15 downto 0);
  signal s_event_reg : t_a_reg(1 downto 0) := (others => std_logic_vector'(others => '0'));

然而，这会产生一个真正的错误:

vcom: error - Error - (vcom-1076) OTHERS choice cannot be used in unconstrained array aggregate.

Answer 1

如何使用类型限定:

signal s_event_reg : t_a_reg(1 downto 0) := (others => std_logic_vector'(others => '0'));
--                                                     ^^^^^^^^^^^^^^^^^