memory - 中断向量中中断处理程序的地址为实际地址的+1

Question

我为 cortex-m3 交叉编译了一个程序。在启动代码中，所有中断都在 g_pfnVectors 中给出。当我反汇编时，在地址 0x0 处，我看到“堆栈指针值”。比在地址 0x4 处给出了复位中断处理程序地址。这与以下系统中断地址保持一致。

这是我的问题:为什么在中断向量中，中断处理程序的地址是实际地址的+1。 ResetISR 处理程序的地址是 0x184，但在中断表中它是 0x185。所有其他中断处理程序地址都是这种情况。这是什么原因？

    00000000 <g_pfnVectors>:
       0:   10008000    andne   r8, r0, r0
       4:   00000185    andeq   r0, r0, r5, lsl #3
       8:   00000215    andeq   r0, r0, r5, lsl r2
       c:   0000021d    andeq   r0, r0, sp, lsl r2

    00000184 <ResetISR>:
     184:   b580        push    {r7, lr}
     186:   b084        sub sp, #16
     188:   af00        add r7, sp, #0
     .......

    00000214 <NMI_Handler>:
     214:   b480        push    {r7}
     216:   af00        add r7, sp, #0
     218:   e7fe        b.n 218 <NMI_Handler+0x4>
     21a:   bf00        nop
     .......
    0000021c <HardFault_Handler>:
     21c:   b480        push    {r7}
     21e:   af00        add r7, sp, #0
     220:   e7fe        b.n 220 <HardFault_Handler+0x4>
     .......

Answer 1

我在 ARMv7-M Architecture Reference Manual, Vector Table Definition(B1.5.3) 部分找到了答案:

The Vector table must be naturally aligned to a power of two whose alignment value is greater than or equal to (Number of Exceptions supported x 4), with a minimum alignment of 128 bytes. On power-on or reset, the processor uses the entry at offset 0 as the initial value for SP_main, see The SP registers on page B1-572. All other entries must have bit[0] set to 1, because this bit defines the EPSR.T bit on exception entry. See Reset behavior on page B1-586 and Exception entry behavior on page B1-587 for more information. On exception entry, if bit[0] of the associated vector table entry is set to 0, execution of the first instruction causes an INVSTATE UsageFault, see The special-purpose program status registers, xPSR on page B1-572 and Fault behavior on page B1-608. If this happens on a reset, this escalates to a HardFault, because UsageFault is disabled on reset, see Priority escalation on page B1-585 for more information.