hardware - 编译器的bug，还是对SystemVerilog的误解？未声明的端口类型在模拟中工作

Question

我有一个带有多个输入逻辑和输出逻辑端口的模块，其中一个端口应该是input foo::bar ，其中 foo 是一个包，而 bar 是一个枚举。但是，我省略了 input，所以它只是普通的 foo::bar。然而，它在仿真中仍然有效(测试通过，您可以在波形上看到值正在正确传输)。

来自 the LRM ，我们有:

inout_declaration ::= 
  inout port_type list_of_port_identifiers 
input_declaration ::= 
  input port_type list_of_port_identifiers 
  | input data_type list_of_variable_identifiers 
output_declaration ::= 
  output port_type list_of_port_identifiers 
  | output data_type list_of_variable_port_identifiers 
interface_port_declaration ::= 
  interface_identifier list_of_interface_identifiers 
  | interface_identifier . modport_identifier list_of_interface_identifiers 
ref_declaration ::= 
  ref data_type list_of_port_identifiers 
port_type ::=  
  [ net_type_or_trireg ] [ signing ] { packed_dimension } 

显然不是 inout_dec、input_dec、output_dec 或 ref_dec。深入了解 LRM，net_type_or_trireg 是 supply0 |供应1 |三 |三重奏 |三重奏 |三零 |三一 |电线 |魔杖 | wor 或 tri，但不是那些。

会不会是一个interface_port_dec？嗯，interface_identifier::= identifier 和 enum_identifier::= identifier。但是，确定 := 不是对称的和可传递的，所以 interface_identifier := enum_identifier 是不正确的。

我在这里错过了什么？

Answer 1

它被定义为一个inout。

参见 IEEE Std 1800-2012 § 23.2.2.3 确定端口类型、数据类型和方向的规则

For the first port in the port list:
— If the direction, port kind, and data type are all omitted, then the port shall be assumed to be a member of a non-ANSI style list_of_ports, and port direction and type declarations shall be declared after the port list.
Otherwise:
— If the direction is omitted, it shall default to inout.
— If the port kind is omitted, it shall be determined as specified below.
— If the data type is omitted, it shall default to logic except for interconnect ports which have no data type.

在一些示例之后的同一部分中，LRM状态:

For subsequent ports in the port list:
— If the direction, port kind and data type are all omitted, then they shall be inherited from the previous port. If the previous port was an interconnect port, this port shall also be an interconnect port.
Otherwise:
— If the direction is omitted, it shall be inherited from the previous port.
— If the port kind is omitted, it shall be determined as specified above.
— If the data type is omitted, it shall default to logic except for interconnect ports that have no data type.