vhdl - 在VHDL中找到运算符 '0'的 “+”定义

Question

首先，我想指出的是，这是我第一次尝试VHDL，请客气。我想读取X1 ... X4输入，并在输出中产生总和。这是我的代码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity counter_of_aces is 
  Generic(N: integer := 3);
     port( X1, X2, X3, X4 : IN BIT; 
        count: out std_logic_vector(N-1 downto 0)); 
end counter_of_aces;

architecture behavioral of counter_of_aces is 
signal counter : std_logic_vector(Ν-1 downto 0);
begin 
  process (X1, X2, X3, X4) 
  begin
    counter <= "0";
    if(X1='1' OR X2='1' OR X3='1' OR X4='1')then 
        counter <= counter + "1"; --O counter λειτουργεί ως στοιχείο μνήμης 
    else
        counter <= counter;
    end if; 
  end process; 
end behavioral;

我得到以下错误

ERROR:HDLCompiler:69 - Line 11: <í> is not declared.
ERROR:HDLCompiler:1731 - Line 17: found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"
ERROR:HDLCompiler:854 - Line 10: Unit <behavioral> ignored due to previous errors.

它指的是哪个“i”，其他的指的是什么？提前致谢。

Answer 1

使用以下命令启动您的VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;