vhdl - 添加 std_logic_vectors 时出错

Question

我想要一个添加两个 std_logic_vectors 的简单模块。但是，在使用代码时
下面的 + 运算符不会合成。

library IEEE; 
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity add_module is
        port(
  pr_in1   : in std_logic_vector(31 downto 0);
  pr_in2   : in std_logic_vector(31 downto 0);
  pr_out   : out std_logic_vector(31 downto 0)  
        );
end add_module;

architecture Behavior of add_module is

begin

    pr_out <= pr_in1 + pr_in2;

end architecture Behavior;

我从 XST 收到的错误消息

第 17 行。+ 在这种情况下不能有这样的操作数。

我想念图书馆吗？如果可能的话，我不想将输入转换为自然数。

非常感谢

Answer 1

您希望编译器如何知道您的 std_logic_vectors 是有符号还是无符号？在这两种情况下，加法器的实现是不一样的，所以你需要明确地告诉编译器你想要它做什么;-)

注意:StackOverflow 中的 VHDL 语法突出显示很糟糕。将此代码复制/粘贴到您首选的 VHDL 编辑器中以更轻松地阅读它。

library IEEE; 
use IEEE.std_logic_1164.all;
-- use IEEE.std_logic_arith.all; -- don't use this
use IEEE.numeric_std.all; -- use that, it's a better coding guideline

-- Also, never ever use IEEE.std_unsigned.all or IEEE.std_signed.all, these
-- are the worst libraries ever. They automatically cast all your vectors
-- to signed or unsigned. Talk about maintainability and strong typed language...

entity add_module is
  port(
    pr_in1   : in std_logic_vector(31 downto 0);
    pr_in2   : in std_logic_vector(31 downto 0);
    pr_out   : out std_logic_vector(31 downto 0)  
  );
end add_module;

architecture Behavior of add_module is
begin

  -- Here, you first need to cast your input vectors to signed or unsigned 
  -- (according to your needs). Then, you will be allowed to add them.
  -- The result will be a signed or unsigned vector, so you won't be able
  -- to assign it directly to your output vector. You first need to cast
  -- the result to std_logic_vector.

  -- This is the safest and best way to do a computation in VHDL.

  pr_out <= std_logic_vector(unsigned(pr_in1) + unsigned(pr_in2));

end architecture Behavior;