verilog - "parameter"和 "localparam"之间的区别

Question

我正在用 Verilog 编写一个项目并想使用 parameter在我的模块中定义一些参数。但是当我阅读一些源代码时，localparam有时用来代替parameter .

他们之间有什么区别？

Answer 1

通常，localparam 背后的想法(添加到 Verilog-2001 标准中)是为了保护 localparam 的值最终用户意外或不正确的重新定义(与 parameter 值不同，此值不能通过参数重新定义或 defparam 语句修改)。

基于 IEEE 1364-2005(第 4.10.2 章):

Verilog HDL local parameters are identical to parameters except that they cannot directly be modified by defparam statements or module instance parameter value assignments. Local parameters can be assigned constant expressions containing parameters, which can be modified with defparam statements or module instance parameter value assignments.

此外，在 SystemVerilog ( IEEE 1800-2012 (ch. 6.20.4)) 中:

Unlike nonlocal parameters, local parameters can be declared in a generate block, package, class body, or compilation-unit scope. In these contexts, the parameter keyword shall be a synonym for the localparam keyword.

Local parameters may be declared in a module’s parameter_port_list. Any parameter declaration appearing in such a list between a localparam keyword and the next parameter keyword (or the end of the list, if there is no next parameter keyword) shall be a local parameter. Any other parameter declaration in such a list shall be a nonlocal parameter that may be overridden.

如果您想了解有关此主题的更多信息，我建议您阅读 Clifford E. Cummings 的论文“ New Verilog-2001 Techniques for Creating Parameterized Models (or Down With `define and Death of a defparam!)”。