performance - L1缓存命中的周期/成本与在x86上注册的周期/成本？

Question

我记得在我的架构类中假设L1缓存命中为1个周期(即与寄存器访问时间相同)，但是在现代x86处理器上实际上是真的吗？

L1缓存命中需要几个周期？与注册访问权限相比如何？

Answer 1

这是一篇很棒的文章:

http://arstechnica.com/gadgets/reviews/2002/07/caching.ars/1

要回答您的问题-是的，缓存命中的成本与寄存器访问的成本大致相同。当然，缓存未命中代价很高；)

PS:

具体情况会有所不同，但是此链接有一些不错的引用数字:

Approximate cost to access various caches and main memory?

Core i7 Xeon 5500 Series Data Source Latency (approximate)
L1 CACHE hit, ~4 cycles
L2 CACHE hit, ~10 cycles
L3 CACHE hit, line unshared ~40 cycles
L3 CACHE hit, shared line in another core ~65 cycles
L3 CACHE hit, modified in another core ~75 cycles remote
L3 CACHE ~100-300 cycles
Local DRAM ~30 ns (~120 cycles)
Remote DRAM ~100 ns 

PPS:

这些数字代表了更老，更慢的CPU，但是比率基本上保持不变:

http://arstechnica.com/gadgets/reviews/2002/07/caching.ars/2

Level                    Access Time  Typical Size  Technology    Managed By
-----                    -----------  ------------  ---------     -----------
Registers                1-3 ns       ?1 KB          Custom CMOS  Compiler
Level 1 Cache (on-chip)  2-8 ns       8 KB-128 KB    SRAM         Hardware
Level 2 Cache (off-chip) 5-12 ns      0.5 MB - 8 MB  SRAM         Hardware
Main Memory              10-60 ns     64 MB - 1 GB   DRAM         Operating System
Hard Disk                3M - 10M ns  20 - 100 GB    Magnetic     Operating System/User