vhdl - modelsim 说 : "near " )": (vcom-1576) expecting IDENTIFIER." while compiling

Question

我刚刚写了这个:

library ieee; 
use ieee.std_logic_1164.all; 

entity and_gate is
 port(
  input_1 : in std_logic; 
  input_2 : in std_logic;
  and_result  : out std_logic;
 );
end and_gate; 

architecture rtl of and_gate is
 signal and_gate : std_logic; 
 begin 
  and_gate <= input_1 and input_2; 
  and_result <= and_gate; 
 end rtl; 

当我编译它时，modelsim 编译器给我这个错误:

** Error: C:/modeltech64_10.5/examples/and_gate.vhd(8): near ")": (vcom-1576) expecting IDENTIFIER.

我搜索并尝试了一些解决方案，但仍然出现错误。

Answer 1

这个

and_result  : out std_logic;

应该是这个

and_result  : out std_logic