syntax-error - 错误(10170): expecting “<=” , or “=” , or “+=” , or “-=” , or “*=” , or “/=” , or “%=” , or “&=” , or “|=” , or “^=” , etc

Question

module accumulator (
    input [7:0] A ,
    input reset,
    input clk,
    output reg carryout,
    output reg overflow,
    output reg [8:0] S,
    output reg HEX0,
    output reg HEX1,
    output reg HEX2,
    output reg HEX3
    );

    reg signA;
    reg signS;
    reg [7:0] magA;
    reg [7:0] magS;
    reg Alarger;

    initial begin
        S = 9'b000000000;
    end

    always_ff @ (posedge clk, posedge reset) begin
        if (reset) begin
            S = 9'b000000000;
        end
        else begin

            begin
            signA <= A[7];              //Is A negative or positive
            signS <= S[7];
            S <= A + S;
            end

            if (signA == 1) begin           //A is negative so magnitude is of 2s compliment
                magA <= (~A[7:0] + 1'b1);
            end
            else begin
                magA <= A;
            end

            if (signS == 1) begin           //sum is negative so magnitude is of 2s compliment
                magS <= (~S[7:0] + 1'b1);
            end
            else begin
                magS <= S;
            end

            if (magA > magS) begin
                Alarger <= 1'b1;        //Magnitude of A is larger than magnitude of sum
            end
            else begin
                Alarger <= 1'b0;
            end

            if ((signA == 1) & (Alarger == 1) & (S[7] == 0)) begin
                overflow <= 1'b1;
            end
            else begin
                overflow <= 1'b0;
            end
            if ((signS == 1) & (Alarger == 0) & (S[7] == 0)) begin
                overflow <= 1'b1;
            end
            else begin
                overflow <= 1'b0;
            end
            if ((signS == 1) & (signA == 1) & (S[7] == 0)) begin
                overflow <= 1'b1;
            end
            else begin
                overflow <= 1'b0;
            end
            if ((signS == 0) & (signA == 0) & (S[7] == 1)) begin
                overflow <= 1'b1;
            end
            else begin
                overflow <= 1'b0;
            end
            if (S[8] == 1) begin            //carryout occurred
                carryout <= 1'b1;
                overflow <= 1'b0;
                S <= 9'b000000000;      //sum no longer valid
            end
            else begin
                carryout <= 1'b0;
            end

            display_hex h1                  //display of A
            (
                .bin            (magA),
                .hexl           (HEX2),
                .hexh           (HEX3)
            );

            display_hex h2                  //display of sum
            (
                .bin            (S[7:0]),
                .hexl           (HEX0),
                .hexh           (HEX1)
            );
        end
    end

endmodule 

我正在尝试制作一个累加器，该累加器将A(可有符号或无符号的8位二进制值)重复添加到总和中。一旦计算出总和，则总和和A应在4个十六进制显示LED上显示值(2个LED用于A，两个LED用于求和)。但是，我很难编译它。我已经搜索了错误代码，它看起来像是语法错误的一般错误，可能有多种含义。

Answer 1

我无法重现确切的错误，但是将display_hex的实例化移到always_ff之外可以解决主要问题:

module accumulator
(
    /* ... */
);
    // ...

    always_ff @ (posedge clk, posedge reset) begin
        /* ... */
    end

    display_hex h1 (
        /* ... */
    );

    display_hex h2 (
        /* ... */
    );
endmodule

另一件事:代码从 initial和 always驱动变量S。这将创建多个驱动程序，并且代码将无法编译。要解决此问题，请完全删除首字母，因为在声明 S时 reset将设置为0，因此不需要它。

要么

您可以将所有逻辑移到初始块中。看起来像这样(但是，这很可能不会合成):

initial begin
    S = 0;

    forever begin
        wait @(posedge clock);

        // Do stuff here ..
    end
end