syntax-error - verilog程序计数器语法错误

Question

所以我在程序计数器测试台上遇到语法错误，无法弄清楚为什么我不断得到
以下verilog源具有语法错误:
“pc_tb.v”，20: token 为“初始”
初始
^

我使用的是最初的错误吗？制作流水线数据路径，这是到目前为止我唯一无法使用的部分

//PC_TB.V USED TO TEST THE PC MODULE
`include"pc.v"
module pc_tb;
wire[15:0]out;
reg stall,hold
reg[9:0]Mux,Haz
reg[7:0]Mem[0:65535];
ProgramCounter g1(stall,hold,Mem,out,Mux,Haz);
initial begin
stall=1'b0
hold=1'b0;
Mem=0;
Mux=9'b000000010;
Haz=9'b000000000;
#5 Mem[2]=1;
#10 hold=1'b1;
#30 halt=1'b1;
#40 
initial
#100 $finish;
end
endmodule

Answer 1

您无法在initial块内声明另一个initial块，因此您需要关闭begin(此处为更正后的代码，请参见注释以进行更正):

//PC_TB.V USED TO TEST THE PC MODULE
`include"pc.v"
`define MEM_SIZE 65535

module pc_tb;
  wire [15:0] out;
  reg stall, hold; // Missing ;
  reg [9:0] Mux, Haz; // Missing ;
  reg [7:0] Mem[0:`MEM_SIZE-1]; // Convert to macro
  integer i;

  ProgramCounter g1(stall, hold, Mem, out, Mux, Haz);

  // First initial block
  initial begin
    stall = 1'b0; // Missing ;
    hold = 1'b0;
    // Canot set unpacked array to 0, need to loop through to set each element
    for (i = 0; i < `MEM_SIZE; i = i + 1) begin
      Mem[i] = 8'd0;
    end
    Mux = 9'b000000010;
    Haz = 9'b000000000;

    #5 Mem[2] = 1;
    #10 hold = 1'b1;
    #30 halt = 1'b1; // halt undeclared, not sure what you meant to do here
    // #40 does nothing here
  end // This end was missing 

  // Second initial block
  initial begin
    #100 $finish; // 100 time units from start, simulation will terminate
  end
endmodule