syntax-error - 从 Vivado 获取 "No such design unit"

Question

我需要有人检查我的代码并给我一个健全性检查。这是用 VHDL 编写的。 Vivado 不断提示错误:

[Synth 8-493] no such design unit 'onesevenseg'

但是，我可以清楚地看到我的项目中的文件，并且项目管理器源窗口正在以正确的方式列出文件。

这是发生错误的行。

digitOne: entity xil_defaultlib.oneSevenSeg port map (switchIn, sevenSegOut);

这是有错误的顶级文件。编译进库 xil_defaultlib .

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity oneSevenSegTop is
    Port ( anodeOut : out STD_LOGIC_VECTOR (0 to 7);
           switchIn : in STD_LOGIC_VECTOR (0 to 3);
           sevenSegOut : out STD_LOGIC_VECTOR (0 to 6));
end oneSevenSegTop;

architecture Behavioral of oneSevenSegTop is
component oneSevenSeg 
    Port ( digitIn : in STD_LOGIC_VECTOR (0 to 3);
           segOut : out STD_LOGIC_VECTOR (0 to 6));
end component;
begin

digitOne: entity xil_defaultlib.oneSevenSeg port map (switchIn, sevenSegOut);

anodeOut <= "00000001";

end Behavioral;

这是上面文件正在实例化的文件，也编译到库 xil_defaultlib中.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity oneSevenSeg is
    Port ( digitIn : in STD_LOGIC_VECTOR (0 to 3);
           segOut : out STD_LOGIC_VECTOR (0 to 6));
end oneSevenSeg;

architecture Behavioral of oneSevenSeg is

begin
process(digitIn)
begin
if digitIn = "0000" then --0
    segOut <= "1000000";
elsif digitIn = "0001" then --1
    segOut <= "1111001";
elsif digitIn = "0010" then --2
    segOut <= "0100100";
elsif digitIn = "0011" then --3
    segOut <= "0110000";
elsif digitIn = "0100" then --4
    segOut <= "0011001";
elsif digitIn = "0101" then --5
    segOut <= "0010010";
elsif digitIn = "0110" then --6
    segOut <= "0000010";
elsif digitIn = "0111" then --7
    segOut <= "1111000";
elsif digitIn = "1000" then --8
    segOut <= "0000000";
elsif digitIn = "1001" then --9
    segOut <= "0011000";
else                   -- error
    segOut <= "0110110";
end if;

end process;

end Behavioral;

Answer 1

用 ghdl 尝试你的两个文件:

% ghdl -a --work=xil_defaultlib onesevenseg.vhdl
% ghdl -a -P. onesevensegtop.vhdl
onesevensegtop.vhdl:17:18: no declaration for "xil_defaultlib"
ghdl: compilation error

因此，问题中列出的第二个设计单元很好地分析到了一个名为 xil_defaultlib 的新工作库中。

第二个分析是针对顶级单元的，-P 标志告诉它在当前位置查找其他库。

并且该分析失败了，因为名称 xil_defaultlib 尚未声明。

IEEE Std 1076-2008, 13.2 设计库:

A library clause defines logical names for design libraries in the host environment. A library clause appears as part of a context clause, either at the beginning of a design unit or within a context declaration.
...
Each logical name defined by the library clause denotes a design library in the host environment.

没有告诉分析器简单的名字 xil_defaultlib引用宿主环境中的库名称的含义未知。

如果前缀不是库逻辑名称，则它必须是设计单元，但在库工作、库 IEEE 或库 std 中不知道该名称:

12.3 可见性:

Visibility is either by selection or direct. A declaration is visible by selection at places that are defined as follows:

a) For a primary unit contained in a library: at the place of the suffix in a selected name whose prefix denotes the library.

在 13.2 中进一步:

Every design unit except a context declaration and package STANDARD is assumed to contain the following implicit context items as part of its context clause:

library STD, WORK; use STD.STANDARD.all;

注意库逻辑名称可以隐式定义也可以显式定义。 xil_defaultlib 没有隐含的定义.

添加一个库子句，使所选名称的前缀为 xil_defaultlib.oneSevenSeg可见的。

这可以在库子句中直接完成，使库逻辑名称 IEEE在未命名的顶级文件中可见:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library xil_defaultlib;

entity oneSevenSegTop is
...

所以我们做出了改变，并且:

% ghdl -a -P. onesevensegtop.vhdl
%

没有错误。