arm - STM32 I-CODE 和 D-CODE 总线

Question

STM32文档说I-CODE和D-CODE总线连接到内部闪存。 I-CODE 总线用于获取指令，D-CODE 总线用于代码存储区域中的数据访问(文字加载)。

问题是为什么使用两个独立的总线？它们能否提供对闪存的同时且绝对独立的访问？

Answer 1

从stm32可以看出RM0090 Reference manual (第73页)，I-CODE和D-CODE总线不能独立访问闪存，但是它们可以独立访问闪存接口(interface):

至于为什么有两个:它们有独立的chaches，而且I-CODE总线实现了预取，这对于数据获取来说是没有用的。引用手册的相关部分(第84页):

Data management

Literal pools are fetched from Flash memory through the D-Code bus during the execution stage of the CPU pipeline. The CPU pipeline is consequently stalled until the requested literal pool is provided. To limit the time lost due to literal pools, accesses through the AHB databus D-Code have priority over accesses through the AHB instruction bus I-Code. If some literal pools are frequently used, the data cache memory can be enabled by setting the data cache enable (DCEN) bit in the FLASH_ACR register. This feature works like the instruction cache memory, but the retained data size is limited to 8 rows of 128 bits.