verilog - 创建不同宽度的脉冲

Question

我编写了以下代码，它产生不同宽度的脉冲。我希望代码根据选择线产生单个脉冲。如果选择行是

00 pulse width = 1 us , 01 pulse width = 10 us . . 11 pulse width = 1000 us

输入时钟为10 Mhz。但根据代码，如果我不提供选择线的任何其他值，我将获得连续脉冲。如何才能实现仅一个脉冲？

    module pulse(input wire [1:0] sel , //selection lines s1 s0
        input clk,
        input rst_n,
        output reg flag,    //for checking conditions
        output reg [13:0] Q,    // output of 14 bit counter
        output reg pulse,   //output pulse
        output reg count);  //also for checking conditions

wire flag_d , count_d;

assign flag_d = ( (sel == 2'b00 | sel == 2'b01 | sel == 2'b10 | sel == 2'b11) && count == 1'b0)? 1'b1 : flag;
assign count_d = ( (sel == 2'b00 | sel == 2'b01 | sel == 2'b10 | sel == 2'b11) && count == 1'b0)? 1'b1 : count;

always @(posedge clk , negedge rst_n)
begin
    if(!rst_n)
    begin
        Q <= 14'h0;
        count <= 1'b0;
        pulse <= 1'b0;
        flag <= 1'b0;
    end
    else
    begin

        flag <= flag_d;
        count <= count_d;

        if(flag)
        begin
            case(sel)
            2'b00: Q <= 14'd11;//count from 11 to 1
            2'b01: Q <= 14'd101;//count from 101 to 1
            2'b10: Q <= 14'd1001;//count from 1001 to 1
            2'b11: Q <= 14'd10001;//count from 10001 to 1
            default: Q <= 14'd0;    
            endcase

            flag <= 1'b0;
        end
        else
        begin
            if(Q != 14'h1 && Q != 14'h0)
            begin
                Q <= Q - 14'h1;
                pulse  <= 1'b1;
            end
            else
            begin
                pulse <= 1'b0;
                count <= 1'b0;
            end
        end  
    end
end 
endmodule

Is this code in a good coding style considering the synthesis and hardware of the circuit? if not than what changes I should apply?..

Answer 1

我无法弄清楚flag_d和count_d的意义。另外 ( (sel == 2'b00 | sel == 2'b01 | sel == 2'b10 | sel == 2'b11) && count == 1'b0) 简化为 (计数 == 1'b0)。 sel 不应该是 Xs 或 Zs。

我认为您想要更像以下的内容:

reg [13:0] next_Q;
always @* begin
  if (Q==0) begin
    case(sel)
    2'b00 : next_Q = 14'd10;
    2'b01 : next_Q = 14'd100;
    2'b10 : next_Q = 14'd1000;
    2'b11 : next_Q = 14'd10000;
    endcase
  end
  else begin
    next_Q = Q - 1;
  end
end
always @(posedge clk, negedge rst_n) begin
  if (!rst_n) begin
    pulse <= 1'b0;
    Q <= 14'd0;
  end
  else begin
    // if (Q==0) pulse <= !pulse; // high and low pulse will have equal if sel is constant
    pulse <= (Q!=0); // or high pulse based on sel, low is one clk
    Q <= next_Q;
  end
end

工作示例:http://www.edaplayground.com/x/GRv