generics - 使用泛型的通用 MUX 和 DEMUX

Question

目前的流程似乎可以解决:

process(sel, X)
begin
    -- set all to 0
    mux_out <= (others => zero);
    -- Set input in correct line
    mux_out(to_integer(unsigned(sel))) <= X;
end process;

我会用TestBench测试更多的案例，并将结果写在这里，再次感谢大家的帮助:)

==== 上一篇文章 =======我已经通过以下 Paebbles 示例实现了 DEMUX:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
use IEEE.NUMERIC_STD.ALL;

entity DeMUX_1toX_N_bits is
  generic (
    PORTS  : POSITIVE  := 4;
    BITS   : POSITIVE  := 8 );
  port (
    sel  : in  STD_LOGIC_VECTOR(integer(ceil(log2(real(PORTS)))) - 1 downto 0);
     X    : in  STD_LOGIC_VECTOR(BITS - 1 downto 0);
    Y    : out  STD_LOGIC_VECTOR((BITS * PORTS) - 1 downto 0)  
    );
end;

architecture rtl of DeMUX_1toX_N_bits is
  type T_SLVV is array(NATURAL range <>) of STD_LOGIC_VECTOR(BITS - 1 downto 0);
  signal mux_out : T_SLVV(PORTS - 1 downto 0);
  begin
  gen : for i in 0 to PORTS - 1 generate
    -- connect Output FLAT VECTOR to the correct T_SLVV lines
     Y(((i + 1) * BITS) - 1 downto (i * BITS)) <=  mux_out(i);
  end generate;

  mux_out(to_integer(unsigned(sel))) <= X;
end;

综合工具告诉我“找到了信号 mux_out<3><6> 的 1 位锁存器。锁存器可能是由不完整的 case 或 if 语句生成的。我们不建议在 FPGA/CPLD 设计中使用锁存器，因为它们可能会导致计时问题。”

所以为了解决这个问题，我应该显式地将“0”分配给所有其他输出位？

再次感谢您的帮助:)这种编码方式非常强大，但也很复杂:)

================== 上一篇文章 ====

我正在作为大学实验室开发一个 VHDL 项目(针对 FPGA)。我陷入了数据大小和端口数量参数化的多路复用器和多路分配器的设计上。特别是我找不到编写动态代码的方法(With/Select 语句？)

我想到的是这样的:

use IEEE.STD_LOGIC_1164.ALL;

entity generic_mux is
GENERIC (  inputs: INTEGER := 4;              -- number of inputs
           size : INTEGER := 8);              -- size of each input
Port (
  -- ???  how can i define the input data ports if i don't know the exact number?
);
end generic_mux;

architecture arc of generic_mux is
begin
  -- how can i use the select as an address? The With/Select needs a         
  -- defined number of cases...
  --   ???
end arc;

预先感谢您的帮助。

Answer 1

使用 VHDL-2008 可以这样做:

library ieee;
use ieee.std_logic_1164.all;

package mux_p is
  type slv_array_t is array (natural range <>) of std_logic_vector;
end package;

package body mux_p is
end package body;


library ieee;
use ieee.std_logic_1164.all;
use work.mux_p;

entity mux is
  generic(
    LEN : natural;   -- Bits in each input
    NUM : natural);  -- Number of inputs
  port(
    v_i   : in  mux_p.slv_array_t(0 to NUM - 1)(LEN - 1 downto 0);
    sel_i : in  natural range 0 to NUM - 1;
    z_o   : out std_logic_vector(LEN - 1 downto 0));
end entity;

architecture syn of mux is
begin
  z_o <= v_i(sel_i);
end architecture;

sel_i 也应该是 std_logic_vector，其长度源自 NUM，但上面显示的是与多路复用器相关的代码.

多路复用器的使用示例可以是:

library ieee;
use ieee.std_logic_1164.all;

entity mdl is
  port(
    a_i   : in  std_logic_vector(1 downto 0);
    b_i   : in  std_logic_vector(1 downto 0);
    c_i   : in  std_logic_vector(1 downto 0);
    sel_i : in  natural;
    z_o   : out std_logic_vector(1 downto 0));
end entity;

architecture syn of mdl is
begin
  mux_e : entity work.mux
    generic map(
      LEN => 2,
      NUM => 3)
    port map(
      v_i(0) => a_i,
      v_i(1) => b_i,
      v_i(2) => c_i,
      sel_i  => sel_i,
      z_o    => z_o);
end architecture;