assembly - 如何在 IBM 中使用显式寻址 (HLASM)

Question

我一直在网上寻找有关显式寻址的信息，但什么也没有，而且有，解释非常模糊。我希望有人能详细解释我，如果可能的话，举例说明。我想知道，索引、基址应该用什么寄存器，位移值应该是多少

示例 8(,4) 或 5(0,5) 或 6(7)

Answer 1

这可能取决于正在执行的指令。请参阅 IBM 的此引用资料以帮助整理详细信息。作为一个老 Z 绩效人士，当人们问起有关绩效的问题时，答案几乎总是“这取决于情况”

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Registers that are not explicitly coded in symbolic assembler language representation of machine instructions, but are nevertheless used by assembled machine instructions, are divided into two categories: Base registers that are implicit in the symbolic addresses specified. (See Addresses.) The registers can be identified by examining the object code or the USING instructions that assign base registers for the source module.

Registers that are used by machine instructions, but do not appear in assembled object code. For double shift and fullword multiply and divide instructions, the odd-numbered register, whose number is one greater than the even-numbered register specified as the first operand.

For Move Long and Compare Logical Long instructions, the odd-numbered registers, whose number is one greater than even-numbered registers specified in the two operands.

For Branch on Index High (BXH) and the Branch on Index Low or Equal (BXLE) instructions, if the register specified for the second operand is an even-numbered register, the next higher odd-numbered register is used to contain the value to be used for comparison.

For Load Multiple (LM, LAM) and Store Multiple (STM, STAM) instructions, the registers that lie between the registers specified in the first two operands.

For extended-precision floating point instructions, the second register of the register pair.

For Compare and Form Codeword (CFC) instruction, registers 1, 2, and 3 are used. > For Translate and Test (TRT) instruction, registers 1 and 2 are used. For Update Tree (UPT) instruction, registers 0-5 are used.

For Edit and Mark (EDMK) instruction, register 1 is used. For certain control instructions, one or more of registers 0-4 and register 14 are used. See "Control Instructions" in the applicable z/Architecture Principles of Operation manual.

For certain input and output instructions, either or both registers 1 and 2 are used. See "Input/Output Instructions" in the applicable z/Architecture Principles of Operation manual. On a processor with a vector facility:

1. For instructions that manipulate long floating-point data in vector registers, the odd-numbered vector registers, whose number is one greater than the even-numbered vector registers specified in each operand.

2. For instructions that manipulate 64 bit signed binary data in vector registers, the odd-numbered vector registers, whose number is one greater than the even-numbered vector registers specified in each operand.