assembly - arm64缓存可以从EL0刷新吗？

Question

我正在阅读一篇学术论文，其中指出“ARM 架构还包含逐出缓存行的指令。但是，这些指令只能在处理器处于提升特权模式时使用。”

这是真的吗？我一直在搜索 ARM 文档，但没有看到任何表明我无法在《ARM Cortex-A 系列程序员指南 for ARMv8-A》第 11.5 章 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/BABJDBHI.html 下从 EL0 执行此操作的内容。

Answer 1

这是可配置的。

来自ARMv8 Architecture Reference Manual ，第 D3-1988 页:

EL0 accessibility to cache maintenance instructions

The SCTLR_EL1.UCI bit enables EL0 access for the DC CVAU, DC CVAC, DC CVAP, DC CIVAC, and IC IVAU instructions. When EL0 use of these instructions is disabled because SCTLR_EL1.UCI == 0, executing one of these instructions at EL0 generates a trap to EL1, that is reported using EC = 0x18.

For these instructions read access permission is required. When the value of SCTLR_EL1.UCI is 1:

• For the DC CVAU, DC CVAC, DC CVAP, and DC CIVAC instructions, if the instruction is executed at EL0 and the address specified in the argument cannot be read at EL0, a Permission fault is generated.
• For the IC IVAU instruction, if the instruction is executed at EL0 and the address specified in the argument cannot be read at EL0, it is IMPLEMENTATION DEFINED whether a Permission fault is generated.

Software can read the CTR_EL0 to discover the stride needed for cache maintenance instructions. The SCTLR_EL1.UCT bit enables EL0 access to the CTR_EL0. When EL0 access to the Cache Type register is disabled, a register access instruction executed at EL0 is trapped to EL1 using EC = 0x18.