verilog - 尝试模拟计数器时出现“非法输出或输入端口”错误

Question

我是verilog HDL新手，数字电路零经验。我从互联网上学到了一两件事，现在我正在尝试写计数器脚本的测试台脚本。我从以下网站获取了计数器脚本:

http://www.asic-world.com/verilog/verilog_one_day2.html#Variable_Assignment

计数器:

module counter(clk,rst,enable,count);
input clk, rst, enable;
output [3:0] count;
reg [3:0] count;

always @(posedge clk or posedge rst) begin 
if (rst) begin
    count <= 0;                 
end 
else begin: COUNT           
        while (enable) begin
            count <= count + 1;
            disable COUNT;
        end
end
end
endmodule

然后我编写了一个测试平台，如下所示:

测试台

// counter test bench
`timescale 1ns/100ps
module counter_tb;
    
    reg clk_in;         // using wire won't let value to change inside initial blcok
    reg rst_in;
    reg enable_in;
    reg[3:0] count_out;
    
    counter counter_uut(.clk(clk_in), .rst(rst_in), .enable(enable_in), .count(count_out));
    
    initial begin
    
        // initialize clock, rst and others
        clk_in = 1'b0;          // clock toggles every 5 ns .... see REF_1
        rst_in = 1'b0;          // always NOT reseting
        enable_in = 1'b1;       // always counting
    end
    
    always begin 
        #5 clk_in =~ clk_in;   // ....saw REF_1
    end
    
endmodule

我收到错误消息:

# ** Error: (vsim-3053) C:/Users/Daniel/Desktop/Verilog_Practice/Couter/Counter_tb.v(10): Illegal output or inout port connection for "port 'count'".

我已经努力了几个小时来尝试解决该错误。谁能告诉我我的测试平台出了什么问题？

Answer 1

reg 仅用于对 always 或 initial block 中的信号进行程序分配。对于连续分配，例如连接到模块输出，请改用wire。变化:

reg[3:0] count_out;

至:

wire [3:0] count_out;