vhdl - 如何使用 numeric_std 添加 std_logic

Question

使用 numeric_std 和 vhdl93，我似乎无法弄清楚如何将 std_logic 信号添加到 std_logic_vector。

library ieee;
use ieee.numeric_std.all;

signal in_a, out1: std_logic_vector(3 downto 0);
signal s1 : std_logic;

out1 <= std_logic_vector(signed(in_a) + s1);

Answer 1

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity add_std_logic is
end entity;

architecture foo of add_std_logic is
   signal in_a, out1: std_logic_vector(3 downto 0);
   signal s1 : std_logic;
   signal s1v:  std_logic_vector(0 to 0);
begin

    s1v <= (others => s1);

    out1 <= std_logic_vector(signed(in_a) + signed(s1v));

end architecture;

architecture fum of add_std_logic is
   signal in_a, out1: std_logic_vector(3 downto 0);
   signal s1 : std_logic;
   subtype s1v is  std_logic_vector(0 to 0);
begin

    out1 <= std_logic_vector(signed(in_a) + ( s1 & ""));

end architecture;

当然，您可以将 in_a、s1 和 out1 移至端口。