verilog - 不能由原语或连续赋值驱动

Question

我得到了

reg OUT; cannot be driven by primitives or continuous assignment.

错误。

计数器模块是:

module Counter(
    input             clk,
    input             clear,
    input             load,
    input             up_down, // UP/~DOWN
    input[3:0]        IN,
    input             count,
    output reg[3:0]   OUT
    );
    always @(posedge clk, negedge clear)
    if (~clear) OUT <= 4'b0000;
    else if(load) OUT <= IN;
    else if(count)
    begin
       if(up_down) OUT <= OUT + 1'b1;
       else OUT <= OUT - 1'b1;
    end
    else OUT <= OUT;
endmodule

测试平台是:

module test;
   .
   .
   .
   reg [3:0] IN;
   reg [3:0] OUT;

   Counter c1(clk, clear, load, up_down, IN, count, OUT);
endmodule

错误出现在 Counter c1(clk, clear, load, up_down, IN, count, OUT); 行。

Answer 1

问题是 test 模块具有以下声明:

reg [3:0] OUT;

reg 不应连接到模块output。

将test中的reg更改为wire，然后确保没有其他信号驱动OUT网络测试:

wire [3:0] OUT;