vhdl - 数组类型不受约束 - VHDL

Question

我为以下 vhdl 代码编写了测试平台:

library ieee;
USE ieee.std_logic_1164.all;
---USE ieee.std_logic_unsigned.all;
use IEEE.numeric_std.all;

entity division3 is
  port(num1, num2 : in std_logic_vector(7 DOWNTO 0);
    quotient : out std_logic_vector(15 DOWNTO 0));
  end division3;

  architecture arch_div3 of division3 is
             signal v_TEST_VARIABLE1 : integer;
             signal v_TEST_VARIABLE2 : integer;
                   begin 
      P3: PROCESS(num1, num2)
       variable n_times: integer:=1;
      begin

        if(num1>num2) then
       v_TEST_VARIABLE1 <= to_integer(unsigned(num1)) ; 
       v_TEST_VARIABLE2 <= to_integer(unsigned(num2)) ;
       L1:loop
         n_times := n_times + 1;
        exit when ((v_TEST_VARIABLE2 -  v_TEST_VARIABLE1)>0);
        v_TEST_VARIABLE1 <= v_TEST_VARIABLE1 - v_TEST_VARIABLE2;
       end loop L1;


    quotient <= std_logic_vector(to_unsigned(n_times-1,quotient'length));

   elsif (num2>num1) then
      v_TEST_VARIABLE1 <= to_integer(unsigned(num1)) ;  
       v_TEST_VARIABLE2 <= to_integer(unsigned(num2)) ;
       L2:loop
        n_times:=n_times+1;
       exit when ((v_TEST_VARIABLE1 -  v_TEST_VARIABLE2)>0);
       v_TEST_VARIABLE2 <= v_TEST_VARIABLE2 - v_TEST_VARIABLE1;

   quotient <= std_logic_vector(to_unsigned(n_times-1,quotient'length));

end loop L2;
    else
      quotient <= x"0001";
    end if;

  end PROCESS P3;
    end arch_div3;

测试平台:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--USE ieee.std_logic_unsigned.all;
use IEEE.numeric_std.all;

-- entity declaration for your testbench.Dont declare any ports here  
ENTITY division3_tb IS 
END division3_tb;

ARCHITECTURE behavior OF division3_tb IS
   -- Component Declaration for the Unit Under Test (UUT)
    COMPONENT test  --'test' is the name of the module needed to be tested.
--just copy and paste the input and output ports of your module as such. 
    port(num1, num2 : in std_logic_vector(7 DOWNTO 0);
    quotient : out std_logic_vector(15 DOWNTO 0));

    END COMPONENT;
   --declare inputs and initialize them
   signal num1 : std_logic_vector := "00000000";
   signal num2 : std_logic_vector := "00000000";
   --declare outputs and initialize them
   signal quotient : std_logic_vector(15 downto 0);
   -- Clock period definitions
   constant clk_period : time := 1 ns;
BEGIN
    -- Instantiate the Unit Under Test (UUT)
   uut: test PORT MAP (
         num1 => num1,
          num2 => num2,
          quotient => quotient
        );       

   -- Clock process definitions( clock with 50% duty cycle is generated here.
   clk_process :process
   begin
        num1 <= "00001000";
        wait for clk_period/2;  --for 0.5 ns signal is '0'.
        num1 <= "00001110";
        wait for clk_period/2;  --for next 0.5 ns signal is '1'.
   end process;
   -- Stimulus process
  stim_proc: process
   begin         
        wait for 7 ns;
        num2 <="00000001";
        wait for 3 ns;
        num2 <="00000010";
        wait for 17 ns;
        num2 <= "00000011";
        wait for 1 ns;
        num2 <= "00000110";
        wait;
  end process;

END;

在编译时，我在架构中遇到错误，说:

** Error: C:/Actel/Libero_v9.1/Model/division3_tb.vhd(19): Array type for 'num1' is not constrained.
** Error: C:/Actel/Libero_v9.1/Model/division3_tb.vhd(20): Array type for 'num2' is not constrained.
** Error: C:/Actel/Libero_v9.1/Model/division3_tb.vhd(55): VHDL Compiler exiting

我对 VHDL 有点陌生。有人可以向我解释数组类型的约束吗？谢谢。

Answer 1

信号声明中缺少范围约束std_logic_vector，所以num1和num2的声明应该是:

signal num1 : std_logic_vector(7 downto 0) := "00000000";
signal num2 : std_logic_vector(7 downto 0) := "00000000";

原因是 std_logic_vector 类型被声明为没有范围(VHDL-2002):

type std_logic_vector is array (natural range <>) of std_logic;

在某些情况下，声明没有范围的对象是合法的(称为无约束)，如函数参数和实体端口，但信号必须用显式范围声明(称为约束)，因为信号是有可能在设计中直接转换成电线。

顺便说一句。你可能想重新审视我之前的一些额外评论 answer ，因为我可以看到division3 模块可能仍有一些改进空间。