verilog - 错误 "procedural assignment to a non-register result is not permitted"

Question

我收到错误

[Synth 8-2576] procedural assignment to a non-register result is not permitted ["lpm_mult.v":29]

我做错了什么？

module lpm_mult (
    dataa, datab,     // multiplicand,multiplier
    sum,              // partial sum 
    clock,            // pipeline clock
    clken,            // clock enable
    aclr,             // asynch clear
    result            // product
);

input  clock;
input  clken;
input  aclr;
input  [31:0] dataa;
input  [31:0] datab;
input  [63:0] sum;
output [63:0] result;

always @ (clken or posedge clock) begin
    if (1==clken) begin
        assign result = dataa * datab;
    end
end

endmodule

Answer 1

还有更多问题然后给出错误消息。正如其他人已经指出的那样result应定义为output <b>reg</b> [63:0] result;

其他问题不会产生编译错误；它们会产生不正确的行为并且无法合成。用代码:

always @ (clken or posedge clock) begin
    if (1==clken) begin
        assign result = dataa * datab;
    end
end

• clken是异步触发；它不应该出现在敏感列表中。

• 安 assign Always block 内的语句称为过程连续赋值。一旦触发分配，它将持续并立即更新 dataa 的任何更改。或datab (忽略 clken 和 clock 的条件)。

  • 注意:IEEE 正在考虑弃用过程连续赋值，因此将来它可能会成为非法语法。 IEEE Std 1800-2012 C.4.2程序赋值和取消赋值语句:

    The procedural assign and deassign statements can be a source of design errors and can be an impediment to tool implementation. The procedural assign and deassign statements do not provide a capability that cannot be done by another method that avoids these problems. Therefore, the procedural assign and deassign statements are on a deprecation list. In other words, a future revision of IEEE Std 1800 might not require support for these statements. This current standard still requires tools to support the procedural assign and deassign statements. However, users are strongly encouraged to migrate their code to use one of the alternate methods of procedural or continuous assignments.

    常规连续赋值( assign 在程序 block 之外)将保留为合法的合法语法。
    Verilog 和 SystemVerilog 已被 IEEE 正式合并为 IEEE Std 1800-2009。

• 同步逻辑应使用非阻塞 ( <= ) 分配。这是同步逻辑 block 中阻塞 ( = ) 赋值的合法语法，但它不会重新开始。在同步逻辑 block 中使用阻塞分配可能会导致模拟器中的竞争条件，从而导致 RTL 和综合电路之间的行为不匹配。

  • 注:assign语句必须使用阻塞赋值(非阻塞是非法语法)。

您的代码应如下所示，以便在模拟中正确编译和运行:

...
output reg [63:0] result;

always @ (posedge clock) begin
    if (clken==1) begin
        result <= dataa * datab;
    end
end