verilog - Verilog中的Z代表什么？

Question

我最近在 Verilog 代码中发现了这样的代码，我指的是编写有限状态机。

reg [15:0]Bus;
Bus = 'bzzzzzzzzzzzz1111;

这里的z是什么意思？

Answer 1

来自 IEEE Std 1800-2012，“6.3.1 逻辑值”部分:

z—represents a high-impedance state

The SystemVerilog value set consists of the following four basic values:

0—represents a logic zero or a false condition
1—represents a logic one or a true condition
x—represents an unknown logic value
z—represents a high-impedance state

The values 0 and 1 are logical complements of one another.