audio - 从 Verilog 到 VHDL 的 Delta-sigma DAC

Question

下面的代码在 Verilog 中实现了 Delta-sigma DAC，来自 Xilinx 应用笔记，我想编写等效的 VHDL 代码。我对 Verilog 一无所知，而且我是 VHDL 的初学者，所以我不得不做出很多猜测，并且可能是初学者错误(代码如下)。我不确定翻译是否正确，有人可以帮忙吗？

原始 Verilog

`timescale 100 ps / 10 ps
`define MSBI 7

module dac(DACout, DACin, Clk, Reset);
output DACout;
reg DACout;
input [`MSBI:0] DACin;
input Clk;
input Reset;

reg [`MSBI+2:0] DeltaAdder;
reg [`MSBI+2:0] SigmaAdder;
reg [`MSBI+2:0] SigmaLatch;
reg [`MSBI+2:0] DeltaB;

always @(SigmaLatch) DeltaB = {SigmaLatch[`MSBI+2], SigmaLatch[`MSBI+2]} << (`MSBI+1);
always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB;
always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;
always @(posedge Clk or posedge Reset)
begin
    if(Reset)
    begin
        SigmaLatch <= #1 1'bl << (`MSBI+1);
        DACout <= #1 1'b0;
    end
    else
    begin
        SigmaLatch <== #1 SigmaAdder;
        DACout <= #1 SigmaLatch[`MSBI+2];
    end
end
endmodule

我在 VHDL 中的尝试:

entity audio is
    generic(
        width  : integer := 8
    );
    port(
        reset  : in    std_logic;
        clock  : in    std_logic;
        dacin  : in    std_logic_vector(width-1 downto 0);
        dacout : out   std_logic
    );
end entity;

architecture behavioral of audio is
    signal deltaadder    : std_logic_vector(width+2 downto 0);
    signal sigmaadder    : std_logic_vector(width+2 downto 0);
    signal sigmalatch    : std_logic_vector(width+2 downto 0);
    signal deltafeedback : std_logic_vector(width+2 downto 0);
begin
    deltafeedback <= (sigmalatch(width+2), sigmalatch(width+2), others => '0');
    deltaadder <= dacin + deltafeedback;
    sigmaadder <= deltaadder + sigmalatch;

    process(clock, reset)
    begin
        if (reset = '1') then
            sigmalatch <= ('1', others => '0');
            dacout <= '0';
        elsif rising_edge(clock) then
            sigmalatch <= sigmaadder;
            dacout <= sigmalatch(width+2);
        end if;
    end process;
end architecture;

Answer 1

看起来您正在使用 ieee.std_logic_unsigned(或 _arith)或两者。

Please don't do that 。请改用 ieee.numeric_std.all。

我的 Verilog 完全不存在，所以我忘记了 Verilog 默认是有符号还是无符号算术...但无论是哪种，都将所有数字信号转换为 signed 或 unsigned 要匹配的类型。

您的重置子句可能需要阅读以下内容:

sigmalatch <= (width+1 => '1', others => '0');

增量反馈更新类似于:

deltafeedback(width+2 downto width+1) <= sigmalatch(width+2) & sigmalatch(width+2);
deltafeedback(width downto 0) <= (others => '0');

最后，为了匹配 Verilog，我认为您的 width 泛型应该称为 MSBI 并设置为 7，(或者更改所有 width+2s 到 width+1s 以符合您对 width 通用的意图)